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PDF LXT381 Data sheet ( Hoja de datos )
| Número de pieza | LXT381 | |
| Descripción | Octal E1 Line Interface Unit | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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LXT381
Octal E1 Line Interface Unit
Datasheet
General Description
The LXT381 is an octal short haul analog Line Interface Unit for ITU G.703 2.048 Mbit/sec.
transmission systems. It incorporates eight independent receivers and eight independent
transmitters in a single LQFP-144 or PBGA-160 package.
The transmit output drivers provide low impedance, constant during marks and spaces and
constant pulse amplitudes independent of supply voltage variations.
The LXT381 may be configured for unbalanced 75Ω or for balanced 120Ω systems without
external component changes in the transmit section. The transmit return loss performance
exceeds latest ETSI return loss recommendations such as ETS 300166.
The LXT381 features a differential data receiver architecture with high noise interference
margin. The receivers use peak detection and a variable threshold for reliable data recovery
down to 500 mV or up to 12 dB of cable attenuation.
Each receiver incorporates an analog Loss Of Signal (LOS) processor that meets latest ITU
G.775 standard.
The fast power down mode of all transmitters allows the implementation of Hitless Protection
Switching (HPS) application without the use of relays.
Applications
s Synchronous Digital Hierarchy (SDH) E1 tributary interfaces
s Public switching trunk line interfaces
s Digital Access Cross Connects (DACS)
s Microwave transmission systems
Product Features
s Octal E1 short haul line interface per ITU
G.703
s Single rail supply voltage of 3.3V with 5V
I/O capability
s Low power consumption of <100 mW per
channel (typ.)
s 75Ω/120Ω TX operation without
component changes
s Transmit return loss complies with ETSI
ETS 300 166
s Hitless Protection Switching (HPS)
s Driver short circuit current limiter (<50 mA
RMS)
s Differential receiver with 15dB of signal to
noise interference margin
s Data recovery with no need for external
reference clock
s Analog LOS detection per ITU G.775
s Simple hardware control mode
s JTAG Boundary Scan test port per IEEE
1149.4
s Small footprint 144 pin LQFP or 160 pin
PBGA package
As of January 15, 2001, this document replaces the Level One document
known as Octal E1 Line Interface.
Order Number: 249005-001
January 2001
1 page  
Octal E1 Line Interface — LXT381
1.0 Pin Assignments and Signal Descriptions
Figure 1. LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and
Package Markings
TPOS7
TCLK7
ALOS6
RNEG6
RPOS6
RCLK6
TNEG6
TPOS6
TCLK6
RPD
GND
GND
GND
GND
GND
GND
VCCIO0
GNDIO0
VCC0
GND0
LOOP0
LOOP1
LOOP2
LOOP3
LOOP4
LOOP5
LOOP6
LOOP7
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1
ALOS1
TCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Part #
LOT #
FPO #
LXT381LE XX
XXXXXX
XXXXXXXX
Rev #
108 TPOS4
107 TCLK4
106 ALOS5
105 RNEG5
104 RPOS5
103 RCLK5
102 TNEG5
101 TPOS5
100 TCLK5
99 TDI
98 TDO
97 TCK
96 TMS
95 TRST
94 AT1
93 AT2
92 VCCIO1
91 GNDIO1
90 VCC1
89 GND1
88 GND
87 GND
86 GND
85 GND
84 GND
83 NC
82 NC
81 TCLK2
80 TPOS2
79 TNEG2
78 RCLK2
77 RPOS2
76 RNEG2
75 ALOS2
74 TCLK3
73 TPOS3
Package Topside Markings
Marking
Part #
Rev #
Lot #
FPO #
Definition
Unique identifier for this product family.
Identifies the particular silicon “stepping” — refer to the specification update for additional stepping
information.
Identifies the batch.
Identifies the Finish Process Order.
Datasheet
5
5 Page 
Octal E1 Line Interface — LXT381
Table 1. LXT381 Pin Description (Continued)
Pin #
LQFP
Pin #
PBGA
Symbol
I/O1
Description
108 B13
109 B12
TPOS4
TNEG4
DI Transmit Positive Data Input.
DI Transmit Negative Data Input.
110 A14
RCLK4
DO Receive Clock Output.
111 A13
112 A12
RPOS4
RNEG4
DO Receive Positive Data Output.
DO Receive Negative Data Output.
113 E11
ALOS4
DO Analog Loss of Signal Output.
114 E14
Output Driver Enable Input.
OE DI If this pin is asserted Low all analog driver outputs immediately enter a high
impedance mode to support redundancy applications without external
mechanical relays. All other internal circuitry stays active.
115 E13
RPOL
Receive Polarity Select Input. Determines RPOS/RNEG polarity.
DI RPOS/RNEG are active High output polarity when RPOL is High and
active Low polarity when RPOL is Low.
116 A11, B11
TVCC4
S Transmit Driver Power Supply. Power supply pin for the output driver.
117 B10
118 A10
TTIP4
TRING4
AO Transmit Tip Output.
AO Transmit Ring Output.
119 A9, B9
TGND4
S Transmit Driver Ground. Ground pin for the output driver.
120 A8
121 B8
RTIP4
RRING4
AI Receive Tip Input.
AI Receive Ring Input.
122 C9, D9
TGND5
S Transmit Driver Ground. Ground pin for the output driver.
123 C10
124 D10
TRING5
TTIP5
AO Transmit Ring Output.
AO Transmit Tip Output.
125 C11, D11
TVCC5
S Transmit Driver Power Supply. Power supply pin for the output driver.
126 D8
127 C8
RRING5
RTIP5
AI Receive Ring Input.
AI Receive Tip Input.
128 C4, D4
TVCC6
S Transmit Driver Power Supply. Power supply pin for the output driver.
129 D5
130 C5
TTIP6
TRING6
AO Transmit Tip Output.
AO Transmit Ring Output.
131 C6, D6
TGND6
S Transmit Driver Ground. Ground pin for the output driver.
132 D7
133 C7
RRING6
RTIP6
AI Receive Ring Input.
AI Receive Tip Input.
134 A6, B6
TGND7
S Transmit Driver Ground. Ground pins for the output driver.
135 B5
136 A5
TTIP7
TRING7
AO Transmit Tip Output.
AO Transmit Ring Output.
137 A4, B4
TVCC7
S Transmit Driver Power Supply. Power supply pin for the output driver.
138 B7
139 A7
RRING7
RTIP7
AI Receive Ring Input.
AI Receive Tip Input.
140 E4
ALOS7
DO Analog Loss of Signal Output.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not
Connected.
Datasheet
11
11 Page | ||
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| PDF Descargar | [ Datasheet LXT381.PDF ] | |
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