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CN8330 데이터시트 PDF




Conexant Systems에서 제조한 전자 부품 CN8330은 전자 산업 및 응용 분야에서
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부품번호 CN8330 기능
기능 DS3/E3 Framer
제조업체 Conexant Systems
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CN8330 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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CN8330 데이터시트, 핀배열, 회로
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The CN8330 is an integral DS3/E3 framer designed to support the transmission
formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751
standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T
PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a
High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing
overhead.
The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751
E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be
enabled to reduce jitter on the incoming data. Transmit and receive data is available to
the host in either serial or parallel byte and nibble formats. Access is provided to the
terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in
T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations
(LCVs), parity errors, and Far End Block Errors (FEBEs).
Two operational modes are available: microprocessor and stand-alone monitor
control modes. The microprocessor control mode monitors all status conditions and
provides configuration control. The stand-alone monitor mode allows the CN8330 to
operate as a monitor providing status and alarm information on external pins.
Distinguishing Features
• Supports DS3/E3 framing modes
• Includes high-speed HDLC controller
(52 MHz)
• Framing recovery for M13, C-bit
parity, Syntran, and G.751 E3 signals
• Serial or parallel (octet or nibble)
interface modes
• Average reframe time of less than
1 ms for DS3 and less than 250 µs
for E3
• Supports the LAPD terminal data link
and FEAC channel as defined in
T1.107a-1989
• 68-pin PLCC or 80-pin MQFP
surface-mount package
• Operates from a single +5 VDC ±5%
power supply
• Low-power CMOS technology
Functional Block Diagram
RXPOS
RXNEG
DS3CKI
TXCKI
M
U
X
Source
Loopback
Unipolar
Conversion
Bypass
FIFO
FIFO
Enable
Framing
Recovery
Overhead/
Data Link
Processing
RXMSY
CBITO
RXCCK
RXDAT
RXCLK
Status
Applications
• Digital PCM switches
• Digital Cross-Connect Systems
• Channel Service Units (CSUs)
• Channel extenders
• ATM Switches/Concentrators
• PBXs
• Switched Multimegabit Digital
Service (SMDS) Equipment
• Test equipment
• Routers (including HSSI ports)
TXPOS
TXNEG
TCLKO
PPDL
Receiver
RDAT[7:0]
RXBCK
M Status
U
X
Bipolar
Framing/
PPDL
TXBCK
Encoder
Overhead
Insertion
Transmitter
TDAT[7:0]
AD[7:0]
Control
Line
Loopback
Microprocessor
Interface
To/From
All Blocks
Overhead/
Data Link
Processing
TXCCK
CBITI
TXCKI
TXDATI
TXSYI
Data Sheet
100441E
October 13, 1999




CN8330 pdf, 반도체, 판매, 대치품
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.4 Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.4.1 Bipolar-to-Unipolar Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.4.2 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.4.3 Received Signal Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.4.4 Framing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.4.5 Alarm Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.4.6 Terminal Data Link Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.4.6.1 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.4.6.2 Receiver Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.4.7 RxFEAC Channel Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.4.8 PPDL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.4.9 PPDLONLY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.4.10 Serial C-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.5 Monitor Mode for Stand-Alone Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.5.1 DS3 Monitor Mode Error Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
0x00—Mode Control Register (CR00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
0x01—Terminal Data Link Control Register (CR01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
0x02—Status Interrupt Control Register (CR02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
0x03—Transmit FEAC Channel Byte (CR03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
0x04—Feature Control Register (CR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
0x05—PPDL Control Register (CR05). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
0x10—DS3/E3 Maintenance Status Register (SR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
0x11—Counter Interrupt Status Register (SR01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x12—Data Link Interrupt Status Register (SR02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
0x13—Receive FEAC Channel Byte (SR03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
0x14—Terminal Data Link Status Register (SR04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x15—Part Number/Hardware Version Register (SR05) . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x16—Shadow Status Register (SR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x20–0x26—DS3/E3 Error Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
0x20—DS3 Parity Error Counter (SR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
0x21—DS3 Disagreement Counter (SR08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
0x22—DS3/E3 Frame Error Counter (SR09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
0x23—DS3 Path Parity Error Counter (SR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
0x24—DS3 FEBE Event Counter (SR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
0x25,0x26—DS3/E3 LCV Counter—Low and High Bytes (SR12,SR13) . . . . . . . . . . . . . 3-13
3.3 Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
0x30–0x37—Transmit Terminal Data Link Message Buffer (TxTDL) . . . . . . . . . . . . . . . . 3-14
0x40–0x47—Receive Terminal Data Link Message Buffer (RxTDL) . . . . . . . . . . . . . . . . 3-14
3.4 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
ii
Conexant
100441E

4페이지










CN8330 전자부품, 판매, 대치품
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
List of Figures
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure A-1.
Figure A-2.
Figure A-3.
Figure A-4.
Figure A-5.
CN8330 Pinout Diagram - 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CN8330 Pinout Diagram - 80-Pin MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
CN8330 Framer Functional Logic Diagram - 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
CN8330 Framer Functional Logic Diagram - 80-Pin MQFP . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Transmitter Line Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Clocked Receiver Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Transmitter Timing for Serial DS3 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Transmitter Timing for Parallel DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Transmitter Timing for Serial E3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
C-Bit Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
PPDL Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Nibble Mode with the PPDLONLY Control Pin Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
VCO Output Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Receiver Timing for Serial DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Receiver Timing for Parallel DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
E3 Receiver Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
PPDL Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
C-Bit Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Monitor Mode Error Indication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Output and Input Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
68–Pin Plastic Leaded Chip Carrier (J-Bend) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
80-Pin Metric Quad Flat Pack (MQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
HDLC Formatter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
HDLC Formatter Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
HDLC Formatter Logic Diagram - 80-Pin MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
PPDL Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
PPDL Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
100441E
Conexant
v

7페이지


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관련 데이터시트

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CN8330

DS3/E3 Framer

Conexant Systems
Conexant Systems

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