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부품번호 ATT3000 기능
기능 (ATT3000 Series) Field-Programmable Gate Arrays
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ATT3000 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
s User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
s Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
s Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with Xilinx* XC3000*
and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
s ORCAFoundry for ATT3000 Development
System support
s All FPGAs processed on a QML-certified line
s Extensive packaging options
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
* Xilinx, XC3000, and XC3100 are registered trademarks of
Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Max
Logic
Gates
1,500
2,000
3,000
4,500
6,000
Typical Gate
Range
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
Configurable
Logic
Blocks
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
20 x 16
User I/Os
Max
64
80
96
120
144
Flip-
Flops
256
360
480
688
928
Horizontal Configuration
Long Lines Data Bits
16 14,779
20 22,176
24 30,784
32 46,064
40 64,160




ATT3000 pdf, 반도체, 판매, 대치품
ATT3000 Series Field-Programmable Gate Arrays
Data Sheet
February 1997
Configuration Memory
The static memory cell used for the configuration mem-
ory in the FPGA has been designed specifically for
high reliability and noise immunity. Integrity of the
FPGA configuration memory based on this design is
ensured even under various adverse conditions. Com-
pared with other programming alternatives, static mem-
ory is believed to provide the best combination of high
density, high performance, high reliability, and compre-
hensive testability.
As shown in Figure 2, the basic memory cell consists of
two CMOS inverters plus a pass transistor used for
writing and reading cell data. The cell is only written to
during configuration and only read from during read-
back. During normal operation, the cell provides contin-
uous control and the pass transistor is off and does not
affect cell stability. This is quite different from the opera-
tion of conventional memory devices, in which the cells
are frequently read and rewritten.
The memory cell outputs Q and Q use full ground and
VCC levels and provide continuous, direct control. The
additional capacitive load and the absence of address
decoding and sense amplifiers provide high stability to
the cell. Due to their structure, the configuration mem-
ory cells are not affected by extreme power supply
excursions or very high levels of alpha particle radia-
tion. Soft errors have not been observed in reliability
testing.
Two methods of loading configuration data use serial
data, while three use byte-wide data. The internal con-
figuration logic utilizes framing information, embedded
in the program data by the ORCA Foundry Develop-
ment System, to direct memory cell loading. The serial
data framing and length count preamble provide pro-
gramming compatibility for mixes of various Lucent pro-
grammable gate arrays in a synchronous, serial, daisy-
chain fashion.
READ OR
WRITE
Q CONFIGURATION
CONTROL
Q
DATA
5-3101(F)
Figure 2. Static Configuration Memory Cell
4 Lucent Technologies Inc.

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ATT3000 전자부품, 판매, 대치품
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Configurable Logic Block
The array of configurable logic blocks (CLBs) provides
the functional elements from which the user’s logic is
constructed. The logic blocks are arranged in a matrix
within the perimeter of IOBs. The ATT3020 has 64 such
blocks arranged in eight rows and eight columns. The
ORCA Foundry Development System is used to com-
pile the configuration data for loading into the internal
configuration memory to define the operation and inter-
connection of each block. User definition of CLBs and
their interconnecting networks may be done by auto-
matic translation from a schematic capture logic dia-
gram or optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-
flops, and an internal control section; see Figure 4
below. There are five logic inputs (.a, .b, .c, .d, and .e);
a common clock input (.k); an asynchronous direct
reset input (.rd); and an enable clock (.ec). All may be
driven from the interconnect resources adjacent to the
blocks. Each CLB also has two outputs (.x and .y)
which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied
from the function F or G outputs of the combinatorial
logic, or the block input, data-in (.di). Both flip-flops in
each CLB share the asynchronous reset (.rd) which,
when enabled and high, is dominant over clocked
inputs. All flip-flops are reset by the active-low chip
input, RESET, or during the configuration process.
The flip-flops share the enable clock (.ec) which, when
low, recirculates the flip-flops’ present states and inhib-
its response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control
inputs and select their sources. The user may also
select the clock net input (.k), as well as its active
sense within each logic block. This programmable
inversion eliminates the need to route both phases of a
clock signal throughout the device. Flexible routing
allows use of common or individual CLB clocking.
The combinatorial logic portion of the logic block uses
a 32 x 1 look-up table to implement Boolean functions.
Variables selected from the five logic inputs and the
two internal block flip-flops are used as table address
inputs. The combinatorial propagation delay through
the network is independent of the logic function gener-
ated and is spike-free for single-input variable changes.
This technique can generate two independent logic
functions of up to four variables each as shown in Fig-
ure 5A, or a single function of five variables as shown in
Figure 5B, or some functions of seven variables as
shown in Figure 5C.
DATA IN
.di
LOGIC
VARIABLES
.a
.b
.c
.d
.e
ENABLE
CLOCK
.ec
CLOCK
DIRECT
RESET
.k
.rd
Lucent Technologies Inc.
QX
F
COMBINATORIAL
FUNCTION
G
QX
“1” (ENABLE)
F
DIN
G
0
MUX
1
F
DIN
G
0
MUX
1
DQ
RD
DQ
RD
QX
.x
F
CLB OUTPUTS
G
.y
QY
“0” (INHIBIT)
(GLOBAL RESET)
Figure 4. Configurable Logic Block
5-3103(F)
7

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(ATT3000 Series) Field-Programmable Gate Arrays

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