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BQ4024 데이터시트 PDF




Benchmarq에서 제조한 전자 부품 BQ4024은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 BQ4024 자료 제공

부품번호 BQ4024 기능
기능 Nonvolatile SRAM
제조업체 Benchmarq
로고 Benchmarq 로고


BQ4024 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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BQ4024 데이터시트, 핀배열, 회로
www.DataSheet4U.com
bq4024/bq4024Y
128Kx16 Nonvolatile SRAM
Features
® Data retention in the absence of
power
® Automatic write-protection dur-
ing power-up/power-down cycles
® Industry-standard 40-pin 128K x
16 pinout
® Conventional SRAM operation;
unlimited write cycles
® 10-year minimum data retention
in absence of power
® Battery internally isolated until
power is applied
General Description
The CMOS bq4024 is a nonvolatile
2,097,152-bit static RAM organized
as 131,072 words by 16 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
limited write cycles of standard
SRAM.
The control circuitry constantly
monitors the single 5V supply for
an out-of-tolerance condition.
When VCC falls out of tolerance, the
SRAM is unconditionally write-
protected to prevent an inadvertent
write operation.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4024 uses extremely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The bq4024 requires no external cir-
cuitry and is compatible with the
industry-standard 2Mb SRAM pin-
out.
Pin Connections
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 WE
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 VSS
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
40-Pin DIP Module
PN402401.eps
Selection Guide
Part
Number
Maximum
Access
Time (ns)
bq4024MA -85
85
bq4024MA -120
120
Pin Names
A0–A16 Address inputs
DQ0–DQ15 Data input/output
CE Chip enable input
OE Output enable input
WE Write enable input
NC No connect
VCC +5 volt supply input
VSS Ground
Block Diagram
Negative
Supply
Tolerance
-5%
-5%
Part
Number
bq4024YMA -85
bq4024YMA -120
Maximum
Access
Time (ns)
85
120
Negative
Supply
Tolerance
-10%
-10%
Sept. 1992
1




BQ4024 pdf, 반도체, 판매, 대치품
bq4024/bq4024Y
AC Test Conditions
Parameter
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
Test Conditions
0V to 3.0V
5 ns
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (TA = 0 to 70°C, VCCmin VCC VCCmax)
Symbol
tRC
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Parameter
Read cycle time
Address access time
Chip enable access time
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-85 -120
Min. Max. Min. Max.
85 - 120 -
- 85 - 120
- 85 - 120
- 45 - 60
5 - 5-
0 - 0-
0 35 0 45
0 25 0 35
10 - 10 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Sept. 1992
4

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BQ4024 전자부품, 판매, 대치품
Write Cycle No. 1 (WE-Controlled) 1,2,3
bq4024/bq4024Y
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
Sept. 1992
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
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관련 데이터시트

부품번호상세설명 및 기능제조사
BQ4024

Nonvolatile SRAM

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BQ4024Y

Nonvolatile SRAM

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