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PDF BQ4024Y Data sheet ( Hoja de datos )
| Número de pieza | BQ4024Y | |
| Descripción | Nonvolatile SRAM | |
| Fabricantes | Benchmarq | |
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bq4024/bq4024Y
128Kx16 Nonvolatile SRAM
Features
® Data retention in the absence of
power
® Automatic write-protection dur-
ing power-up/power-down cycles
® Industry-standard 40-pin 128K x
16 pinout
® Conventional SRAM operation;
unlimited write cycles
® 10-year minimum data retention
in absence of power
® Battery internally isolated until
power is applied
General Description
The CMOS bq4024 is a nonvolatile
2,097,152-bit static RAM organized
as 131,072 words by 16 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
limited write cycles of standard
SRAM.
The control circuitry constantly
monitors the single 5V supply for
an out-of-tolerance condition.
When VCC falls out of tolerance, the
SRAM is unconditionally write-
protected to prevent an inadvertent
write operation.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4024 uses extremely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The bq4024 requires no external cir-
cuitry and is compatible with the
industry-standard 2Mb SRAM pin-
out.
Pin Connections
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 WE
38 A16
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 VSS
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
40-Pin DIP Module
PN402401.eps
Selection Guide
Part
Number
Maximum
Access
Time (ns)
bq4024MA -85
85
bq4024MA -120
120
Pin Names
A0–A16 Address inputs
DQ0–DQ15 Data input/output
CE Chip enable input
OE Output enable input
WE Write enable input
NC No connect
VCC +5 volt supply input
VSS Ground
Block Diagram
Negative
Supply
Tolerance
-5%
-5%
Part
Number
bq4024YMA -85
bq4024YMA -120
Maximum
Access
Time (ns)
85
120
Negative
Supply
Tolerance
-10%
-10%
Sept. 1992
1
1 page  
Read Cycle No. 1 (Address Access) 1,2
bq4024/bq4024Y
Read Cycle No. 2 (CE Access) 1,3,4
Read Cycle No. 3 (OE Access) 1,5
Notes:
Sept. 1992
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
5
5 Page 
Notes
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet BQ4024Y.PDF ] | |
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