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CS42888 데이터시트 PDF




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부품번호 CS42888 기능
기능 8-Out CODEC
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CS42888 데이터시트, 핀배열, 회로
www.DataSheet4U.com
CS42888
108 dB, 192 kHz 4-In, 8-Out CODEC
FEATURES
 Four 24-bit A/D, Eight 24-bit D/A Converters
 ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
 DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
 ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
 Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
 System Sampling Rates up to 192 kHz
 Programmable ADC High-Pass Filter for DC
Offset Calibration
 Logarithmic Digital Volume Control
 I²C® & SPIHost Control Port
 Supports Logic Levels Between 5 V and 1.8 V
 Popguard® Technology
GENERAL DESCRIPTION
The CS42888 CODEC provides four multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of operation with ei-
ther differential or single-ended inputs and outputs, in a
64-pin LQFP package.
Four fully differential, or single-ended, inputs are avail-
able on stereo ADC1 and ADC2. Digital volume control
is provided for each ADC channel, with selectable over-
flow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42888 is available in a 64-pin LQFP package in
Commercial (-10° to +70°) and Automotive (-40° to
+105°) grades. The CDB42888 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 61 for complete ordering
information.
The CS42888 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Digital Supply =
3.3 V to 5 V
I2C/SPI
Software Mode
Control Data
Interrupt
Reset
Register
Configuration
ADC Overflow
& Clock Error
Interrupt
Analog Supply =
3.3 V to 5 V
Internal Voltage
Reference
External
Mute Control
Mute
Control
Serial Audio
Input
Auxilliary Serial
Audio Input
Input Master
Clock
Serial Audio
Output
Volume
Controls
Digital
Filters
∆Σ
Modulators
High Pass
Filter
High Pass
Filter
Digital
Filters
Digital
Filters
Multibit
DAC1-4 and
8
Differential or
Single-Ended
Analog Filters
Outputs
8
Multibit
Oversampling
ADC1
Multibit
Oversampling
ADC2
2
2 Differential or Single-
Ended Analog Inputs
2
2
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS717F1




CS42888 pdf, 반도체, 판매, 대치품
CS42888
7.1.1 Passive Input Filter ................................................................................................................ 52
7.1.2 Passive Input Filter w/Attenuation ......................................................................................... 52
7.2 DAC Output Filter ........................................................................................................................... 53
8. ADC FILTER PLOTS............................................................................................................................. 54
9. DAC FILTER PLOTS............................................................................................................................. 56
10. PARAMETER DEFINITIONS............................................................................................................... 58
11. REFERENCES..................................................................................................................................... 59
12. PACKAGE INFORMATION................................................................................................................. 60
12.1 Thermal Characteristics ............................................................................................................. 60
13. ORDERING INFORMATION ............................................................................................................... 61
14. REVISION HISTORY ........................................................................................................................... 61
LIST OF FIGURES
Figure 1.Typical Connection Diagram ......................................................................................................... 9
Figure 2.Output Test Circuit for Maximum Load ....................................................................................... 16
Figure 3.Maximum Loading ....................................................................................................................... 16
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 18
Figure 5.TDM Serial Audio Interface Timing ............................................................................................. 18
Figure 6.Serial Audio Interface Master Mode Timing ................................................................................ 19
Figure 7.Serial Audio Interface Slave Mode Timing .................................................................................. 20
Figure 8.Control Port Timing - I²C Format ................................................................................................. 21
Figure 9.Control Port Timing - SPI Format ................................................................................................ 22
Figure 10.Full-Scale Input ......................................................................................................................... 25
Figure 11.Audio Output Initialization Flow Chart ....................................................................................... 26
Figure 12.Full-Scale Output ...................................................................................................................... 28
Figure 13.De-Emphasis Curve .................................................................................................................. 29
Figure 14.I²S Format ................................................................................................................................. 31
Figure 15.Left-Justified Format ................................................................................................................. 31
Figure 16.Right-Justified Format ............................................................................................................... 31
Figure 17.One-Line Mode #1 Format ........................................................................................................ 31
Figure 18.One-Line Mode #2 Format ........................................................................................................ 32
Figure 19.TDM Format .............................................................................................................................. 32
Figure 20.AUX I²S Format ......................................................................................................................... 33
Figure 21.AUX Left-Justified Format ......................................................................................................... 33
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 34
Figure 23.Control Port Timing, I²C Write ................................................................................................... 35
Figure 24.Control Port Timing, I²C Read ................................................................................................... 35
Figure 25.Single-to-Differential Active Input Filter ..................................................................................... 51
Figure 26.Single-Ended Active Input Filter ................................................................................................ 51
Figure 27.Passive Input Filter ................................................................................................................... 52
Figure 28.Passive Input Filter w/Attenuation ............................................................................................. 52
Figure 29.Active Analog Output Filter ....................................................................................................... 53
Figure 30.Passive Analog Output Filter .................................................................................................... 53
Figure 31.SSM Stopband Rejection .......................................................................................................... 54
Figure 32.SSM Transition Band ................................................................................................................ 54
Figure 33.SSM Transition Band (Detail) ................................................................................................... 54
Figure 34.SSM Passband Ripple .............................................................................................................. 54
Figure 35.DSM Stopband Rejection .......................................................................................................... 54
Figure 36.DSM Transition Band ................................................................................................................ 54
Figure 37.DSM Transition Band (Detail) ................................................................................................... 55
Figure 38.DSM Passband Ripple .............................................................................................................. 55
Figure 39.QSM Stopband Rejection ......................................................................................................... 55
Figure 40.QSM Transition Band ................................................................................................................ 55
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CS42888 전자부품, 판매, 대치품
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
DAC_SCLK
DAC_LRCK
AUX_LRCK
AUX_SCLK
AUX_SDIN
AOUT1 +,-
AOUT2 +,-
AOUT3 +,-
AOUT4 +,-
AOUT5 +,-
AOUT6 +,-
AOUT7 +,-
AOUT8 +,-
MUTEC
AGND
VQ
VA
AIN1 +,-
AIN2 +,-
AIN3 +,-
AIN4 +,-
FILT+_DAC
FILT+_ADC
TSTN
INT
SCL/CCLK
SDA/CDOUT
CS42888
17
16
15
DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
14
18
DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input fre-
quency must be 256xFs in the TDM digital interface format.
DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
19 active on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital
interface format.
20
Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently
active on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs.
21 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
22
Auxiliary Serial Input (Input) - Provides an additional serial input for two’s complement serial
audio data. Used only in the TDM digital interface format.
26, 25
27, 28
30, 29
31, 32 Differential Analog Output (Output) - The full-scale analog output level is specified in the Ana-
34, 33 log Characteristics table. Each leg of the differential outputs may also be used single-ended.
36, 37
38, 39
40, 41
35
Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and
pops that can occur in any single supply system.
42, 56 Analog Ground (Input) - Ground reference for the analog section.
43 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
44, 53
Analog Power (Input) - Positive power supply for the analog section. See “Digital I/O Pin Char-
acteristics” on page 8.
46, 45
48, 47
50, 49
52, 51
Differential Analog Input (Input) - Signals are presented differentially or single-ended to the
Delta-Sigma modulators. The full-scale input level is specified in the Analog Characteristics
specification table.
54
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits of the DAC.
55
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
cuits of the ADC.
57, 58 Test In - This pin is an input used for test purposes only. It must be tied to ground for normal
59, 60 operation.
Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the
61 ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt regis-
ter.
63 Serial Control Port Clock (Input) - Serial clock for the control port interface.
64 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data.
DS717F1
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부품번호상세설명 및 기능제조사
CS42888

8-Out CODEC

Cirrus Logic
Cirrus Logic

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