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부품번호 | CS44600 기능 |
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기능 | 6-Channel Digital Amplifier Controller | ||
제조업체 | Cirrus Logic | ||
로고 | |||
전체 30 페이지수
www.DataSheet4U.com
CS44600
6-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
– Eliminates Clock Jitter Effects
– Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces
Modulation Energy
PWM PopGuard® for Single-Ended Mode
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
– +24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI and I²C Host Control Interfaces
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
PS_SYNC
XTI
XTO
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
INT
PWM
Clock
Control
Auto Fs
Detect
DAI
Serial
Port
SRC
Volume
/ Limiter
Volume
/ Limiter
Volume
/ Limiter
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Power
Supply
Rejection
PWM
Conversion
PWM
Conversion
PWM
Conversion
PSR_RESET
PSR_EN
PSR_MCLK
PSR_SYNC
PSR_DATA
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
SPI/I2C Host
Control Port
PWM
Backend
Control/
Status
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY '05
DS633PP1
CS44600
7.1.1 Increment (INCR) ................................................................................................ 48
7.1.2 Memory Address Pointer (MAPx) ....................................................................... 48
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................... 48
7.2.1 Chip I.D. (Chip_IDx) ............................................................................................ 48
7.2.2 Chip Revision (Rev_IDx) ..................................................................................... 48
7.3 Clock Configuration and Power Control (address 02h) ................................................... 49
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ......................................................... 49
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ..................................... 49
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0]) ............................ 49
7.3.4 Power Down XTAL (PDN_XTAL) ........................................................................ 49
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE) ......................................... 50
7.3.6 Power Down (PDN) ............................................................................................. 50
7.4 PWM Channel Power Down Control (address 03h) ........................................................ 50
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1) ............................ 50
7.5 Misc. Configuration (address 04h) ................................................................................... 51
7.5.1 Digital Interface Format (DIFX) ........................................................................... 51
7.5.2 AM Frequency Hopping (AM_FREQ_HOP) ........................................................ 51
7.5.3 Freeze Controls (FREEZE) ................................................................................. 51
7.5.4 De-Emphasis Control (DEM[1:0]) ....................................................................... 52
7.6 Ramp Configuration (address 05h) ................................................................................. 52
7.6.1 Ramp-Up/Down Setting (RAMP[1:0]) ................................................................ 52
7.6.2 Ramp Speed (RAMP_SPD[1:0]) ......................................................................... 52
7.7 Volume Control Configuration (address 06h) .................................................................. 53
7.7.1 Single Volume Control (SNGVOL) ...................................................................... 53
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0]) ................................................... 53
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) ............................... 53
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR) .............................................. 54
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR) ................................. 54
7.7.6 Auto-Mute (AMUTE) ........................................................................................... 54
7.8 Master Volume Control - Integer (address 07h) .............................................................. 55
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) .......................................... 55
7.9 Master Volume Control - Fraction (address 08h) ............................................................. 55
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0]) ....................................... 55
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh) ....................................... 57
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) ...................................... 57
7.11 Channel XX Volume Control1 - Fraction (address 11h) .............................................. 57
7.12 Channel XX Volume Control2 - Fraction (address 12h) ................................................ 57
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0]) ................................... 57
7.13 Channel Mute (address 13h) ......................................................................................... 58
7.13.1 Independent Channel Mute (CHXX_MUTE) ..................................................... 58
7.14 Channel Invert (address 14h) ........................................................................................ 58
7.14.1 Invert Signal Polarity (CHXX_INV) .................................................................... 58
7.15 Peak Limiter Control Register (address 15h) ............................................................... 59
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) .................................................... 59
7.15.2 Peak Signal Limiter Enable (LIMIT_EN) ........................................................... 59
7.16 Limiter Attack Rate (address 16h) ................................................................................ 59
7.16.1 Attack Rate (ARATE[7:0]) ................................................................................. 59
7.17 Limiter Release Rate (address 17h) ........................................................................... 60
7.17.1 Release Rate (RRATE[7:0]) .............................................................................. 60
7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
...................................................................................................................................... 60
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0]) ................. 60
7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)
...................................................................................................................................... 61
4 DS633PP1
4페이지 CS44600
LIST OF TABLES
Table 1. Common DAI_MCLK Frequencies.................................................................................. 24
Table 2. DAI Serial Audio Port Channel Allocations ..................................................................... 26
Table 3. Load Compensation Example Settings ........................................................................... 31
Table 4. Typical PWM Switch Rate Settings................................................................................. 33
Table 5. Digital Audio Interface Formats....................................................................................... 51
Table 6. Master Integer Volume Settings...................................................................................... 55
Table 7. Master Fractional Volume Settings ................................................................................. 56
Table 8. Channel Integer Volume Settings ................................................................................... 57
Table 9. Channel Fractional Volume Settings............................................................................... 58
Table 10. Limiter Attack Rate Settings.......................................................................................... 60
Table 11. Limiter Release Rate Settings....................................................................................... 60
Table 12. Channel Load Compensation Filter Coarse Adjust ....................................................... 61
Table 13. Channel Load Compensation Filter Fine Adjust............................................................ 61
Table 14. PWM Minimum Pulse Width Settings............................................................................ 68
Table 15. Differential Signal Delay Settings.................................................................................. 68
Table 16. Channel Delay Settings................................................................................................. 68
Table 17. Power Supply Sync Clock Divider Settings................................................................... 70
Table 18. Decimator Shift/Scale Coefficient Calculation Examples .............................................. 71
Table 19. Revision History ............................................................................................................ 77
DS633PP1
7
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부품번호 | 상세설명 및 기능 | 제조사 |
CS44600 | 6-Channel Digital Amplifier Controller | Cirrus Logic |
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