Datasheet.kr   

CS4525 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS4525은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS4525 자료 제공

부품번호 CS4525 기능
기능 30 W Digital TV Amplifier
제조업체 Cirrus Logic
로고 Cirrus Logic 로고


CS4525 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 70 페이지수

미리보기를 사용할 수 없습니다

CS4525 데이터시트, 핀배열, 회로
www.DataSheet4U.com
CS4525
30 W Digital TV Amplifier with Integrated ADC
Digital Amplifier Features
! Fully Integrated Power MOSFETs
! No Heatsink Required
– Programmable Power Foldback on
Thermal Warning
– High Efficiency (85%)
! > 100 dB Dynamic Range
! < 0.1% THD+N @ 1 W
! Configurable Outputs (10% THD+N)
– 1 x 30 W into 4 Ω, Parallel Full-Bridge
– 2 x 15 W into 8 , Full-Bridge
– 2 x 7 W into 4 , Half-Bridge + 1 x 15 W
into 8 , Full-Bridge
! Built-In Protection with Error Reporting
– Overcurrent/Undervoltage/Thermal
Overload Shutdown
– Thermal Warning Reporting
! PWM Popguard® for Half-Bridge Mode
! Click Free Start-Up
! Programmable Channel Delay for System
Noise & Radiated Emissions Management
ADC Features
! Stereo, 24-bit, 48 kHz Conversion
! Multi-bit Architecture
! 95 dB Dynamic Range (A-wtd)
! -88 dB THD+N
! 2 Vrms Input Supports SCART
System Features
! Asynchronous 2-Channel Digital Serial Port
! 32 kHz to 96 kHz Input Sample Rates
! Operation with On-Chip Oscillator Driver or
Applied SYS_CLK at 18.432, 24.576 or
27.000 MHz
! Integrated Sample Rate Converter (SRC)
– Eliminates Clock-Jitter Effects
– Input Sample Rate Independent Operation
– Simplifies System Integration
! Spread Spectrum PWM Modulation
– Reduces EMI Radiated Energy
! Low Quiescent Current
(Features continued on page 2)
System Clock
Crystal Driver
I/O
Stereo
Analog In
Serial Audio
Clocks & Data
Serial Audio
Data I/O
Serial Audio
Clocks & Data
HP Detect/Mute
Reset
Interrupt
I²C or Hardware
Configuration
Crystal Oscillator Driver
Multi-bit ∆Σ ADC
Serial Audio Input Port
Serial Audio
Delay Interface
Auxiliary Serial Port
Register /Hardware
Configuration
2.5 V to 5 V
Audio
Processing
Parametric EQ
High-Pass
Bass/Treble
Adaptive
Loudness
Compensation
2-Ch Mixer
2.1 Bass Mgr
Linkwitz-Riley
Crossover
De-Emphasis
Volume
PWM
Multi-bit ∆Σ
Modulator
with
Integrated
Sample Rate
Converter
Error Protection
Thermal Warning
Thermal Feedback
Over Current
Under Voltage
Gate
Drive
10.5 V to 18 V
VP
Amplifier
Out 1
Gate
Drive
Amplifier
Out 2
Gate
Drive
Gate
Drive
Amplifier
Out 3
Amplifier
Out 4
PGND
PWM Modulator
Output 1
PWM Modulator
Output 2
Advance Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS726A1




CS4525 pdf, 반도체, 판매, 대치품
CS4525
6.1.9 Interrupt Reporting ................................................................................................................ 48
6.1.10 Automatic Power Stage Shut-Down ................................................................................... 48
6.2 Hardware Mode ............................................................................................................................. 49
6.2.1 System Clocking ................................................................................................................... 49
6.2.2 Power-Up and Power-Down ................................................................................................. 49
6.2.2.1 Recommended Power-Up Sequence ....................................................................... 49
6.2.2.2 Recommended Power-Down Sequence .................................................................. 49
6.2.3 Input Source Selection .......................................................................................................... 50
6.2.4 PWM Channel Delay ............................................................................................................ 50
6.2.5 Digital Signal Flow ................................................................................................................ 51
6.2.5.1 High-Pass Filter ........................................................................................................ 51
6.2.5.2 Mute Control ............................................................................................................. 51
6.2.5.3 Warning and Error Reporting .................................................................................... 51
6.2.6 Thermal Foldback ................................................................................................................. 52
6.2.7 Automatic Power Stage Shut-Down ..................................................................................... 53
6.3 PWM Modulators and Sample Rate Converters ............................................................................ 53
6.4 Output Filters ................................................................................................................................. 54
6.4.1 Half-Bridge Output Filter ....................................................................................................... 54
6.4.2 Full-Bridge Output Filter (Stereo or Parallel) ........................................................................ 55
6.5 Analog Inputs ................................................................................................................................. 56
6.6 Serial Audio Interfaces ................................................................................................................... 57
6.6.1 I²S Data Format .................................................................................................................... 57
6.6.2 Left-Justified Data Format .................................................................................................... 57
6.6.3 Right-Justified Data Format .................................................................................................. 58
6.7 I²C Control Port Description and Timing ........................................................................................ 59
7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 60
7.1 Power Supply, Grounding .............................................................................................................. 60
7.1.1 Integrated VD Regulator ....................................................................................................... 60
7.2 QFN Thermal Pad .......................................................................................................................... 60
8. REGISTER QUICK REFERENCE ........................................................................................................ 61
9. REGISTER DESCRIPTIONS ................................................................................................................ 64
9.1 Clock Configuration (Address 01h) ................................................................................................ 64
9.1.1 SYS_CLK Output Enable (EnSysClk) ................................................................................... 64
9.1.2 SYS_CLK Output Divider (DivSysClk) .................................................................................. 64
9.1.3 Clock Frequency (ClkFreq[1:0]) ............................................................................................ 64
9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) ......................................................... 65
9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) .................................................................................. 65
9.1.6 Modulator Phase Shifting (PhaseShift) ................................................................................. 65
9.1.7 AM Frequency Shifting (FreqShift) ....................................................................................... 65
9.2 Input Configuration (Address 02h) ................................................................................................. 66
9.2.1 Input Source Selection (ADC/SP) ......................................................................................... 66
9.2.2 ADC High-Pass Filter Enable (EnAnHPF) ............................................................................ 66
9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only ............................................................ 66
9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) ............................................................ 66
9.3 AUX Port Configuration (Address 03h) .......................................................................................... 67
9.3.1 Enable Aux Serial Port (EnAuxPort) ..................................................................................... 67
9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) ......................................................... 67
9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) .................................................. 67
9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) ................................................. 67
9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) .................................................... 68
9.4 Output Configuration Register (Address 04h) ............................................................................... 68
9.4.1 Output Configuration (OutputCfg[1:0]) .................................................................................. 68
9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) .............................................................. 68
9.4.3 Channel Delay Settings (OutputDly[3:0]) .............................................................................. 68
4 DS726A1

4페이지










CS4525 전자부품, 판매, 대치품
CS4525
Figure 18.Foldback Process ..................................................................................................................... 39
Figure 19.2-Channel Full-Bridge PWM Output Delay ............................................................................... 46
Figure 20.3-Channel PWM Output Delay .................................................................................................. 46
Figure 21.Typical SYS_CLK Input Clocking Configuration ....................................................................... 49
Figure 22.Hardware Mode PWM Output Delay ......................................................................................... 50
Figure 23.Hardware Mode Digital Signal Flow .......................................................................................... 51
Figure 24.Foldback Process ..................................................................................................................... 52
Figure 25.Output Filter - Half-Bridge ......................................................................................................... 54
Figure 26.Output Filter - Full-Bridge .......................................................................................................... 55
Figure 27.Recommended Unity Gain Input Filter ...................................................................................... 56
Figure 28.Recommended 2 VRMS Input Filter ........................................................................................... 56
Figure 29.I²S Serial Audio Formats ........................................................................................................... 57
Figure 30.Left-Justified Serial Audio Formats ........................................................................................... 57
Figure 31.Right-Justified Serial Audio Formats ......................................................................................... 58
Figure 32.Control Port Timing, I²C Write ................................................................................................... 59
Figure 33.Control Port Timing, I²C Read ................................................................................................... 59
LIST OF TABLES
Table 1. I/O Power Rails ........................................................................................................................... 12
Table 2. Bass Shelving Filter Corner Frequencies .................................................................................... 31
Table 3. Treble Shelving Filter Corner Frequencies ................................................................................. 32
Table 4. Bass Management Cross-Over Frequencies .............................................................................. 35
Table 5. 2-Way Cross-Over Frequencies .................................................................................................. 41
Table 6. Auxiliary Serial Port Data Output ................................................................................................ 42
Table 7. PWM Power Output Configurations ............................................................................................ 43
Table 8. PWM Logic-Level Output Configurations .................................................................................... 44
Table 9. PWM Output Switching Rates and Quantization Levels ............................................................. 47
Table 10. SYS_CLOCK Frequency Selection ........................................................................................... 49
Table 11. Input Source Selection .............................................................................................................. 50
Table 12. Serial Audio Interface Format Selection .................................................................................... 50
Table 13. Thermal Foldback Enable Selection ......................................................................................... 52
Table 14. PWM Output Switching Rates and Quantization Levels ........................................................... 53
Table 15. Low-Pass Filter Components - Half-Bridge ............................................................................... 54
Table 16. DC-Blocking Capacitors Values - Half-Bridge ........................................................................... 54
Table 17. Low-Pass Filter Components - Full-Bridge ............................................................................... 55
Table 18. Input Source Selection .............................................................................................................. 60
DS726A1
7

7페이지


구       성 총 70 페이지수
다운로드[ CS4525.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
CS452

(CS452 / CS453) 2.4A/4.4A Injector Solenoid Driver

Cherry Semiconductor Corporation
Cherry Semiconductor Corporation
CS4525

30 W Digital TV Amplifier

Cirrus Logic
Cirrus Logic

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵