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PDF MGSF2P02HD Data sheet ( Hoja de datos )
| Número de pieza | MGSF2P02HD | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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MGSF2P02HD
Power MOSFET
2 Amps, 20 Volts
P−Channel TSOP−6
This device represents a series of Power MOSFETs which are
capable of withstanding high energy in the avalanche and
commutation modes and the drain−to−source diode has a very low
reverse recovery time. These devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
Features
• Miniature TSOP−6 Surface Mount Package − Saves Board Space
• Low Profile for Thin Applications such as PCMCIA Cards
• Very Low RDS(on) Provides Higher Efficiency and Expands
Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Diode is Characterized for Use in Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperatures
• Avalanche Energy Specified
• Package Mounting Information Provided
http://onsemi.com
VDSS
20 V
RDS(ON) TYP
175 mΩ
ID MAX
2.0 A
P−Channel
1256
3
4
1
TSOP−6
CASE 318G
STYLE 1
MARKING
DIAGRAM
3V
W
3V = Device Code
W = Work Week
PIN ASSIGNMENT
Drain Drain Source
6 54
© Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 2
1 23
Drain Drain Gate
ORDERING INFORMATION
Device
Package
Shipping†
MGSF2P02HDT1 TSOP−6 3000 Tape & Reel
MGSF2P02HDT3 TSOP−6 10,000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 Publication Order Number:
MGSF2P02HD/D
1 page  
MGSF2P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
800
Ciss VDS = 0 V VGS = 0 V
TJ = 25°C
600
Crss
400
Ciss
200 Coss
Crss
0
−10 0
VGS VDS
10
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
http://onsemi.com
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