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PDF CS5010-40 Data sheet ( Hoja de datos )
| Número de pieza | CS5010-40 | |
| Descripción | DES/3DES Encryption/Decryption Cores | |
| Fabricantes | Amphion | |
| Logotipo |  |
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CS5010-40
DES/3DES Encryption/Decryption Cores
TM
Virtual Components for the Converging World
The CS5010-CS5040 DES/3DES Encryption/Decryption cores are designed to achieve data privacy in digital
broadband, wireless, and multimedia systems. These high performance application specific silicon cores support
the Data Encryption Standard (also referred as Data Encryption Algorithm) as described in the NIST Federal
Information Processing Standard 46-3. They offer an efficient means of providing both DES and Triple DES
encryption and decryption in one core in order to rapidly construct complete security solutions. The DES/3DES
family of cores are available in both ASIC and programmable logic versions that have been hand crafted by
Amphion to deliver high performance while minimizing power consumption and silicon area.
Patient
Room
Camera
Nurse
Station
PC
MPEG-2
Encoder
MPEG-2
Decoder
Security
Gateway
High Speed
DES/3DES
Encoder
10/100-Base
T-Hub
SeNcuurrsiety
GSattaetwioany
HighPSCpeed
DES/3DES
Decoder
Figure 1: Example of a Secure Audio/Video Based Remote Patient Monitoring System Using DES/3DES
ENCRYPTION CORE FEATURES
Table 1: CS5010-40 Features at a Glance
CS5010
CS5020
Ultra Compact Compact
CS5030
High
Speed
Fully compliant with DES NIST FIPS 46-3
DES and Triple DES Support
32-bit I/O
128-bit I/O
•
•
•
••
••
••
28-bit Key Input Port
56-bit Key Input Port
• ••
EDE2 and EDE3 Triple DES
(112- or 168-bit key length)
• ••
CS5040
Ultra HIgh
Speed
•
•
•
•
•
Optimized for
Amphion continues to expand its family of application-specific cores
See http://www.amphion.com for a current list of products
1
1 page  
TM
Signal
D
DADDR
DLOAD
KEY
KADDR
KLOAD
MODE
TRIPLE
EDE
CLK
RST
DSTAT
QSTRB
QADDR
Q
Table 2: CS5010-40 DES/3DES Cores Interface Signal Definitions
I/O Width (Bits)
Description
I 32 (64 Ultra High Speed) Input Plaintext/Ciphertext data
I 1 (Ultra Compact)
2 (Compact)
3 (High Speed)
0 (Ultra High Speed)
Input Plaintext/Ciphertext data address, 0: the lowest 32-bit word
I 1 Load input Plaintext/Ciphertext enable
I 28 (56 Ultra High Speed) Encryption key data
I 2 Encryption key address, 0: the lowest 28-bit word
I 1 Load encryption key
I 1 Encryption/Decryption mode select, 0: Encryption. 1: Decryption
I 1 DES/3DES mode select, 0: DES, 1:3DES
I 1 Triple DES key selection mode, 0:EDE2, 1: EDE3
I 1 System clock, rising edge active
I 1 Asynchronous reset
O 1 Input port status
This signal will be Asserted when the core is ready for loading the
highest word of the next 64-bit data block, or the highest word of the
multiple input DES blocks available in the Compact or High Speed
cores. The lower words can be loaded at anytime in the period
when DSTAT is LOW depending on the key-size selection
O 1 Output strobe indicating the Plaintext/Ciphertext word Q is valid
O 1 (Ultra Compact)
2 (Compact)
3 (High Speed)
0 (Ultra High Speed)
Output Plaintext/Ciphertext data address, 0: the lowest 32-bit word
O 32 (64 Ultra High Speed) Output Plaintext/Ciphertext data
Optimized for
5
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