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PDF CS5014 Data sheet ( Hoja de datos )
| Número de pieza | CS5014 | |
| Descripción | (CS5012A - CS5016) SELF CALIBRATING A/D CONVERTERS | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS5014 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS5012A CS5014 CS5016
16-, 14-, & 12-bit Self-calibrating A/D Converters
Features
z Monolithic CMOS A/D Converters
– Microprocessor Compatible
– Parallel & Serial Output
– Inherent Track/Hold Input
z True 12-bit, 14-bit, and 16-bit Precision
z Conversion Times
– CS5016: 16.25 µs
– CS5014: 14.25 µs
– CS5012A: 7.20 µs
z Linearity Error: ±0.001% FS
– Guaranteed No Missing Codes
z Self-calibration Maintains Accuracy
– Accurate Over Time & Temperature
z Low Power Consumption
– 150 mW
z Low Distortion
I
Description
The CS5012A/14/16 are 12-, 14-, and 16-bit mono-
lithic analog to digital converters with conversion
times of 7.2 µs, 14.25 µs and 16.25 µs. Unique self-
calibration circuitry ensures excellent linearity and
differential nonlinearity, with no missing codes. Off-
set and full-scale errors are kept within 1/2 LSB
(CS5012A/14) and 1 LSB (CS5016), eliminating the
need for calibration. Unipolar and bipolar input
ranges are digitally selectable.
The pin compatible CS5012A/14/16 consist of a
DAC, conversion and calibration microcontroller,
oscillator, comparator, microprocessor-compatible
3-state I/O, and calibration circuitry. The input
track-and-hold, inherent to the devices’ sampling
architecture, acquires the input signal after each
conversion using a fast-slewing, on-chip buffer am-
plifier. This allows throughput rates up to
100 kSps(CS5012A), 56 kSps (CS5014), and
50 kSps (CS5016).
ORDERING INFORMATION
See “Ordering Information” on page39.
HOLD CS RD A0 BP/UP RST BW INTRLV CAL EOT EOC SCLK SDATA
1 24 25 26 27 36 37 38 39 41 42 43 44
CLKIN 23
REFBUF 32
VREF 31
AIN 29
AGND 30
Clock
Generator
Control
-
Calibration
Memory
Microcontroller
+
- Charge
+
Redistribution
-
DAC +
- Comparator
+ Status Register
28 34 12 40 11 35
VA+ VA- VD+ VD- DGND TST
2
3
4
5
6
7
8
10
14
16
17
18
19
20
21
22
D0 (LSB) CS5016
D1
D2 (LSB) CS5014
D3
D4 (LSB) CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUG ‘05
DS14F9
1 page  
CS5012A CS5014 CS5016
CS5014
CS5014 ANALOG CHARACTERISTICS (continued)
CS5014
Parameter*
Min Typ Max
Specified Temperature Range
Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
Unipolar Mode
Bipolar Mode
(Note 4)
Conversion & Throughput
Conversion Time -14 (Notes 5 and 6)
-40 to +85
25
100
275 375
165 220
14.25
Acquisition Time -14
(Note 6)
3.0 3.75
Throughput
-14
(Note 6)
55.6
Power Supplies
DC Power Supply Currents
IA+
IA-
ID+
ID-
Power Dissipation
Power Supply Rejection
Positive Supplies
Negative Supplies
(Note 7)
(Note 7)
(Note 8)
9 19
-9 -19
36
-3 -6
120 250
84
84
Units
°C
ns
ps
pF
pF
µs
µs
kSps
mA
mA
mA
mA
mW
dB
dB
DS14F89
2-115
5 Page 
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
AIN
VREF
AGND
C C/2 C/4
CS5012A:
CS5014:
CS5016:
Bit 11
Bit 13
Bit 15
MSB
Bit 10
Bit 12
Bit 14
Bit 9
Bit 11
Bit 13
C/8 CS5012A X = 2048 C/X
CS5014 X = 8192
CS5016 X = 32768
C/X
Bit 8
Bit 10
Bit 12
Bit 0 Dummy
LSB
C tot = C + C/2 + C/4 + ... + C/X
Figure 1. Charge Redistribution DAC
S1
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
A unique charge redistribution architecture is
used to implement the successive approximation
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
vice is not calibrating or converting, all capacitors
are tied to AIN forming Ctot. Switch S1 is closed
and the charge on the array, Qin, tracks the input
signal Vin (Figure 2a).
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capaci-
tor array and creates a floating node at the
comparator’s input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
AIN +
V-in
Qin
Ctot
S1
To MCU
DS14F89
-Qin = Vin Ctot
Figure 2a. Tracking Mode
VREF
AGND
D . C tot
S1
Qin
+
V-fn
To MCU
(1-D) C tot
Vin
D = VREF for Vfn = 0V
Figure 2b. Convert Mode
2-171
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5014.PDF ] | |
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