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PDF AT91SAM7XC256 Data sheet ( Hoja de datos )
| Número de pieza | AT91SAM7XC256 | |
| Descripción | (AT91SAM7XC128 / AT91SAM7XC256) Thumb-based Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
– 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes
– 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (AT91SAM7XC256)
– 32 Kbytes (AT91SAM7XC128)
• Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
• Power Management Controller (PMC)
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
Idle Mode
– Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
• Two Parallel Input/Output Controllers (PIO)
– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
AT91 ARM®
Thumb®-based
Microcontrollers
AT91SAM7XC256
AT91SAM7XC128
Summary
Preliminary
6209AS–ATARM–20-Oct-05
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
1 page  
4. Signal Description
AT91SAM7XC256/128 Preliminary
Table 4-1. Signal Description List
Signal Name
VDDIN
VDDOUT
VDDFLASH
VDDIO
VDDCORE
VDDPLL
GND
XIN
XOUT
PLLRC
PCK0 - PCK3
TCK
TDI
TDO
TMS
JTAGSEL
ERASE
NRST
TST
DRXD
DTXD
IRQ0 - IRQ1
FIQ
PA0 - PA30
PB0 - PB30
Function
Type
Power
Voltage Regulator and ADC Power
Supply Input
Power
Voltage Regulator Output
Power
Flash and USB Power Supply
Power
I/O Lines Power Supply
Power
Core Power Supply
Power
PLL Power
Ground
Ground
Clocks, Oscillators and PLLs
Main Oscillator Input
Input
Main Oscillator Output
Output
PLL Filter
Input
Programmable Clock Output
Output
ICE and JTAG
Test Clock
Input
Test Data In
Input
Test Data Out
Output
Test Mode Select
Input
JTAG Selection
Input
Flash Memory
Flash and NVM Configuration Bits Erase
Command
Input
Reset/Test
Microcontroller Reset
I/O
Test Mode Select
Debug Receive Data
Debug Transmit Data
External Interrupt Inputs
Fast Interrupt Input
Parallel IO Controller A
Parallel IO Controller B
Input
Debug Unit
Input
Output
AIC
Input
Input
PIO
I/O
I/O
Active
Level
High
Low
High
Comments
3V to 3.6V
1.85V
3V to 3.6V
3V to 3.6V
1.65V to 1.95V
1.65V to 1.95V
No pull-up resistor
No pull-up resistor.
No pull-up resistor.
Pull-down resistor.
Pull-down resistor
Pull-Up resistor, Open Drain
Output
Pull-down resistor
Pulled-up input at reset
Pulled-up input at reset
6209AS–ATARM–20-Oct-05
5
5 Page 
AT91SAM7XC256/128 Preliminary
7. I/O Lines Considerations
7.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations.
7.2 Test Pin
The TST pin is used for manufacturing test or fast programming mode of the
AT91SAM7XC256/128 when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
7.3 Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
7.4 ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing
time is 200 ms.
7.5 PIO Controller Lines
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma-
ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be
driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while
the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be
taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at
reset.
6209AS–ATARM–20-Oct-05
11
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| PDF Descargar | [ Datasheet AT91SAM7XC256.PDF ] | |
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