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PDF PEB2045 Data sheet ( Hoja de datos )
| Número de pieza | PEB2045 | |
| Descripción | Memory Time Switch CMOS | |
| Fabricantes | Siemens Semiconductor | |
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Memory Time Switch CMOS
(MTSC)
PEB 2045
PEF 2045
Preliminary Data
CMOS IC
1 Features
q Time/space switch for 2048-, 4096- or 8192-kbit/s PCM
systems
q Switching of up to 512 incoming PCM channels to up to
256 outgoing PCM channels
q 16-input and 8-output PCM lines
q Different kinds of modes (2048, 4096, 8192 kbit/s or mixed
mode)
q Configurable for primary access and standard applications
q Programmable clock shift with half clock step resolution for
input and output in primary access configuration
q Configurable for a 4096- and 8192-kHz device clock
q Tristate function for further expansion and tandem
operation
q Tristate control signals for external drivers in primary
access configuration
q 2048-kHz clock output in primary access configuration
q Space switch mode
q 8-bit µP interface
q Single + 5 V power supply
q Advanced low power CMOS technology
q Pin and software compatible to the PEB 2040
P-LCC-44
P-DIP-40
Type
PEB 2045-N
PEB 2045-P
PEF 2045-N
PEF 2045-P
Version
VA3
VA3
VA3
VA3
Ordering Code
Q67100-H8602
Q67100-H8322
Q67100-H6055
Q67100-H6056
Package
P-LCC-44 (SMD)
P-DIP-40
P-LCC-44 (SMD)
P-DIP-40
Semiconductor Group
1
01.94
1 page  
1.2 Functional Symbol
PEB 2045
PEF 2045
Figure 1
Functional Symbol for the Standard Configuration
Figure 2
Functional Symbol for the Primary Access Configuration
Semiconductor Group
5
5 Page 
PEB 2045
PEF 2045
2 Functional Description
The PEx 2045 is a memory time switch device. It can connect any of 512 PCM input channels to any
of 256 output channels.
The input information of a complete frame is stored in the on-chip 4-Kbit speech memory SM (see
figure 8). The incoming 512 channels of 8 bits each are written in sequence into fixed positions in
the SM. This is controlled by the input counter in the timing control block with a 8-kHz repetition rate.
For outputting, the connection memory (CM) is read in sequence. Each location in CM points to a
location in the speech memory. The byte in this speech memory location is read into the current
output time-slot. The read access of the CM is controlled by the output counter which also resides
in the timing control block.
Hence the CM needs to be programmed beforehand for the desired connection. The CM address
corresponds to one particular output time-slot and line number. The contents of this CM-address
points to a particular input time-slot and line number (now resident in the SM).
The PEx 2045 works in standard configuration for usual switching applications, and in the primary
access configuration where it realizes, together with the PEB 2035 (ACFA) and the PEB 2235
(IPAT), the system interface for up to four primary multiplex access lines.
In the following chapters the functions of the PEx 2045 will be covered in more detail.
Semiconductor Group
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PEB2045.PDF ] | |
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