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U63716 데이터시트 PDF




ZMD에서 제조한 전자 부품 U63716은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 U63716 자료 제공

부품번호 U63716 기능
기능 CAPSTORE 2K X 8 NVSRAM
제조업체 ZMD
로고 ZMD 로고


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U63716 데이터시트, 핀배열, 회로
www.DataSheet4U.com
U63716
CapStore 2K x 8 nvSRAM
Features
Description
S CMOS non- volatile static RAM
2048 x 8 bits
S 70 ns Access Time
S 35 ns Output Enable Access Time
S ICC = 15 mA at 200 ns Cycle Time
S Unlimited Read and Write Cycles
to SRAM
S Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
S Software initiated STORE
S Automatic STORE Timing
S 106 STORE cycles to EEPROM
S 100 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Software RECALL Initiation
S Unlimited RECALL cycles from
EEPROM
S Single 5 V ± 10 % Operation
S Operating temperature range:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S ESD protection > 2000 V
(MIL STD 883C M3015.7)
S RoHS compliance and Pb- free
S Package: PDIP24 (600 mil)
The U63716 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In non-volatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U63716 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integra-
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U63716 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63716 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 PDIP
7 24
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
April 7, 2005
1




U63716 pdf, 반도체, 판매, 대치품
U63716
DC Characteristics
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Output Leakage Current
High
Low
High at Three-State- Output
Low at Three-State- Output
Symbol
Conditions
VOH
VOL
IOH
IOL
IIH
IIL
IOHZ
IOLZ
VCC
IOH
IOL
VCC
VOH
VOL
VCC
VIH
VIL
VCC
VOH
VOL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
C-Type
Min. Max.
K-Type
Min. Max.
Unit
2.4 2.4
0.4 0.4
V
V
-4 -4 mA
8 8 mA
1 1 µA
-1 -1 µA
1 1 µA
-1 -1 µA
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
Alt. IEC
1 Read Cycle Timef
2 Address Access Time to Data Validg
3 Chip Enable Access Time to Data Valid
4 Output Enable Access Time to Data Valid
5 E HIGH to Output in High-Zh
6 G HIGH to Output in High-Zh
7 E LOW to Output in Low-Z
8 G LOW to Output in Low-Z
9 Output Hold Time after Address Change
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tELICCH
tEHICCL
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
tPU
tPD
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
Min.
70
5
0
3
0
4
Max.
70
70
35
25
25
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 7, 2005

4페이지










U63716 전자부품, 판매, 대치품
Nonvolatile Memory Operations
Mode Selection
U63716
E
W
A10 - A0
(hex)
Mode
I/O
HX
LH
LL
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
LH
LH
000
Read SRAM
Output Data
555
Read SRAM
Output Data
2AA
Read SRAM
Output Data
7FF
Read SRAM
Output Data
0F0
Read SRAM
Output Data
70F
Nonvolatile STORE
Output High Z
000
Read SRAM
Output Data
555
Read SRAM
Output Data
2AA
Read SRAM
Output Data
7FF
Read SRAM
Output Data
0F0
Read SRAM
Output Data
70E
Nonvolatile RECALL
Output High Z
Power
Standby
Active
Active
Active
Active
Notes
m
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
l: Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G VIL.
No.
PowerStore
Power Up RECALL
Symbol
Alt. IEC
24 Power Up RECALL Durationn
tRESTORE
25 STORE Cycle Durationf, e
tPDSTORE
26 Time allowed to Complete SRAM Cyclef tDELAY
Low Voltage Trigger Level
VSWITCH
n: tRESTORE starts from the time VCC rises above VSWITCH.
Conditions
Min. Max. Unit
650 µs
10 ms
1 µs
4.0 4.5 V
April 7, 2005
7

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