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PDF U63764 Data sheet ( Hoja de datos )
| Número de pieza | U63764 | |
| Descripción | CapStore 8K x 8 nvSRAM | |
| Fabricantes | Simteh | |
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Obsolete - Not Recommended for New Designs
U63764
CapStore 8K x 8 nvSRAM
Features
Description
• CMOS non- volatile static RAM The U63764 has two separate
8192 x 8 bits
modes of operation: SRAM mode
• 70 ns Access Time
and nonvolatile mode. In SRAM
• 35 ns Output Enable Access Time mode, the memory operates as an
•
•
ICC = 15 mA at 200 ns Cycle Time
Unlimited Read and Write Cycles
ordinary static RAM. In non-volatile
operation, data is transferred in
to SRAM
• Automatic STORE to EEPROM
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using charge
mode SRAM functions are disab-
stored in an integrated capacitor
• Software initiated STORE
• Automatic STORE Timing
• 105 STORE cycles to EEPROM
• 10 years data retention in
led.
The U63764 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
• Unlimited RECALL cycles from
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
EEPROM
• Single 5 V ± 10 % Operation
• Operating temperature range:
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
0 to 70 °C
using charge stored in an integra-
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
(MIL STD 883C M3015.7)
• RoHS compliance and Pb- free
• Package: PDIP28 (600 mil)
automatically on power up. The
U63764 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63764 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 PDIP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0055
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU (10)
STANDBY
tdis(E) (5)
tPD (11)
tdis(G) (6)
Output Data Valid
U63764
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tcW
tw(W)
tWLEH tsu(W)
tAVEL
tsu(A)
tAVEH tsu(A-WH)
tsu(E)
tELEH
tw(E)
tDVEH tsu(D)
tEHDX
th(D)
tEHAX
th(A)
tdis(W)
ten(W)
Min.
70
55
55
0
55
55
55
30
0
0
5
March 31, 2006
STK Control #ML0055
5
Rev 1.0
Max.
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 Page 
U63764
Device Operation
The U63764 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
SRAM READ and WRITE operations that are in pro-
gress after an automatic STORE cycle on power down
is requested are given time to complete before the
STORE operation is initiated.
During tDELAY multiple SRAM READ operations may
take place. If a WRITE is in progress it will be allowed a
time, tDELAY, to complete. Any SRAM WRITE cycles
requested after the VCC pin drops below VSWITCH will be
inhibited.
Automatic RECALL
SRAM READ
The U63764 performs a READ cycle whenever E and
G are LOW and W is HIGH. The address specified on
pins A0 - A12 determines which of the 8192 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
Automatic STORE
During normal operation, the U63764 will draw current
from VCC to charge up an integrated capacitor. This
stored charge will be used by the chip to perform a sin-
gle STORE operation. If the voltage on the VCC pin
drops below VSWITCH, the part will automatically discon-
nect the internal components from the external power
supply with a typical delay of 150 ns and initiate a
STORE operation with tPDSTORE max. 10 ms.
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the U63764 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U63764 software controlled STORE cycle is initia-
ted by executing sequential READ cycles from six spe-
cific address locations. By relying on READ cycles only,
the U63764 implements nonvolatile operation while
remaining compatible with standard 8K x 8 SRAMs.
During the STORE cycle, an erase of the previous non-
volatile data is performed first, followed by a parallel
programming of all the nonvolatile elements. Once a
STORE cycle is initiated, further inputs and outputs are
disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read addresses 0000 (hex) Valid READ
2. Read addresses 1555 (hex) Valid READ
3. Read addresses 0AAA (hex) Valid READ
4. Read addresses 1FFF (hex) Valid READ
5. Read addresses 10F0 (hex) Valid READ
6. Read addresses 0F0F (hex) Initiate STORE
Cycle
March 31, 2006
STK Control #ML0055
11
Rev 1.0
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet U63764.PDF ] | |
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