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U63764 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 U63764
기능 CapStore 8K x 8 nvSRAM
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U63764 데이터시트, 핀배열, 회로
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Obsolete - Not Recommended for New Designs
U63764
CapStore 8K x 8 nvSRAM
Features
Description
CMOS non- volatile static RAM The U63764 has two separate
8192 x 8 bits
modes of operation: SRAM mode
70 ns Access Time
and nonvolatile mode. In SRAM
35 ns Output Enable Access Time mode, the memory operates as an
ICC = 15 mA at 200 ns Cycle Time
Unlimited Read and Write Cycles
ordinary static RAM. In non-volatile
operation, data is transferred in
to SRAM
Automatic STORE to EEPROM
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using charge
mode SRAM functions are disab-
stored in an integrated capacitor
Software initiated STORE
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
led.
The U63764 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
EEPROM
Single 5 V ± 10 % Operation
Operating temperature range:
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
0 to 70 °C
using charge stored in an integra-
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
(MIL STD 883C M3015.7)
RoHS compliance and Pb- free
Package: PDIP28 (600 mil)
automatically on power up. The
U63764 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63764 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 PDIP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0055
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0




U63764 pdf, 반도체, 판매, 대치품
U63764
DC Characteristics
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Output Leakage Current
High
Low
High at Three-State- Output
Low at Three-State- Output
Symbol
Conditions
VOH
VOL
IOH
IOL
IIH
IIL
IOHZ
IOLZ
VCC
IOH
IOL
VCC
VOH
VOL
VCC
VIH
VIL
VCC
VOH
VOL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
C-Type
K-Type
Unit
Min. Max. Min. Max.
2.4 2.4
0.4 0.4
V
V
-4 -4 mA
8 8 mA
1 1 μA
-1 -1 μA
1 1 μA
-1 -1 μA
SRAM Memory Operations
No.
Switching Characteristics
Read Cycle
Symbol
Alt. IEC
1 Read Cycle Timef
2 Address Access Time to Data Validg
3 Chip Enable Access Time to Data Valid
4 Output Enable Access Time to Data Valid
5 E HIGH to Output in High-Zh
6 G HIGH to Output in High-Zh
7 E LOW to Output in Low-Z
8 G LOW to Output in Low-Z
9 Output Hold Time after Address Change
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tELICCH
tEHICCL
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
tPU
tPD
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
Min.
70
5
0
3
0
Max.
70
70
35
25
25
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STK Control #ML0055
4
Rev 1.0
March 31, 2006

4페이지










U63764 전자부품, 판매, 대치품
Nonvolatile Memory Operations
Mode Selection
U63764
E
W
A12 - A0
(hex)
Mode
I/O
HX
X
Not Selected
Output High Z
LH
X
Read SRAM
Output Data
LL
X
Write SRAM
Input Data
LH
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
LH
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
Active
Notes
m
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
l: Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G VIL.
No.
PowerStore
Power Up RECALL
Symbol
Alt. IEC
24 Power Up RECALL Durationn
tRESTORE
25 STORE Cycle Durationf, e
tPDSTORE
26 Time allowed to Complete SRAM Cyclef tDELAY
Low Voltage Trigger Level
VSWITCH
n: tRESTORE starts from the time VCC rises above VSWITCH.
Conditions
Min. Max. Unit
650 μs
10 ms
1 μs
4.0 4.5 V
March 31, 2006
STK Control #ML0055
7
Rev 1.0

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부품번호상세설명 및 기능제조사
U63764

CapStore 8K x 8 nvSRAM

Simteh
Simteh

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