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PDF SY100H606 Data sheet ( Hoja de datos )
| Número de pieza | SY100H606 | |
| Descripción | REGISTERED HEX TTL-TO-PECL | |
| Fabricantes | Micrel Semiconductor | |
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REGISTERED HEX
TTL-TO-PECL
SY10H606
SY100H606
FEATURES
DESCRIPTION
s Differential 50Ω ECL outputs
s Choice between differential PECL or TTL clock input
s Single +5V power supply
s VBB output for single-ended use
s Multiple power and ground pins to minimize noise
s Specified within-device skew
s Fully compatible with Motorola MC10H/100H606
s Available in 28-pin PLCC package
The SY10/100H606 are 6-bit, registered, single supply
TTL-to-PECL translators. The devices feature differential
PECL outputs as well as a choice between either a
differential PECL clock input or a TTL clock input. The
asynchronous master reset control is a PECL level input.
With its differential ECL outputs and TTL inputs, the
H606 device is ideally suited for the transmit function of
a HPPI bus-type board-to-board interface application. The
on-chip registers simplify the task of synchronizing the
data between the two boards.
The device is available in either ECL standard: the
10H device is compatible with 10K logic levels, while the
100H device is compatible with 100K logic levels.
BLOCK DIAGRAM
PIN CONFIGURATION
Dn
CLK
CLK
TCLK
MR
VBB
1 OF 6 BITS
DQ
CLK
R
25 24 23 22 21 20 19
D0 26
Qn TCLK 27
18 Q5
17 Q5
Qn
VBB
28
16 Q4
CLK
CLK
1
2
TOP VIEW
PLCC
15 Q4
14 VCCE
MR 3
13 Q3
VCCE
4
12 Q3
5 6 7 8 9 10 11
PIN NAMES
Pin
D0 – D5
CLK, CLK
TCLK
MR
Q0 – Q5
Q0 – Q5
VCCE
VCCT
GND
VBB
1
Function
TTL Data Inputs
Differential PECL Clock Inputs
TTL Clock Input
PECL Master Reset Input
True PECL Outputs
Inverted PECL Outputs
PECL VCC (5.0V)
TTL VCC (5.0V)
TTL/PECL Ground
VBB Reference Output (PECL)
Rev.: D Amendment: /0
Issue Date: March, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100H606.PDF ] | |
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