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PDF SY100H607 Data sheet ( Hoja de datos )
| Número de pieza | SY100H607 | |
| Descripción | REGISTERED HEX PECL-TO-TTL | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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REGISTERED HEX
PECL-TO-TTL
SY10H607
SY100H607
FEATURES
s Differential PECL data and clock inputs
s 48mA sink, 15mA source TTL outputs
s Single +5V power supply
s Multiple power and ground pins to minimize noise
s Specified within-device skew
s VBB output for single-ended use
s Fully compatible with Motorola MC10H/100H607
s Available in 28-pin PLCC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100H607 are 6-bit, registered, dual supply
PECL-to-TTL translators. The devices feature differential
PECL inputs for both data and clock. The TTL outputs
feature 48mA sink, 15mA source drive capability for
driving high fanout loads. The asynchronous master reset
control is a PECL level input.
With its differential PECL inputs and TTL outputs, the
H607 device is ideally suited for the receive function of a
HPPI bus-type board-to-board interface application. The
on-chip registers simplify the task of synchronizing the
data between the two boards.
The device is available in either ECL standard: the
10H device is compatible with 10K logic levels, while the
100H device is compatible with 100K logic levels.
PIN CONFIGURATION
Dn
Dn
CLK
CLK
MR
VBB
1 OF 6 BITS
DQ
CLK
R
25 24 23 22 21 20 19
Qn Q2 26
18 D5
Q1 27
17 D5
Q0
TGND
CLK
28
1
2
TOP VIEW
PLCC
16 D4
15 D4
14 VCCE
CLK 3
13 D3
VBB
4
12 D3
5 6 7 8 9 10 11
PIN NAMES
Pin
D0 – D5
D0 – D5
CLK, CLK
MR
Q0 – Q5
VCCE
VCCT
TGND
EGND
VBB
1
Function
True PECL Data Inputs
Inverted PECL Data Inputs
Differential PECL Clock Input
PECL Master Reset Input
TTL Outputs
PECL VCC (5.0V)
TTL VCC (5.0V)
TTL Ground
PECL Ground
VBB Reference Output (PECL)
Rev.: F Amendment: /1
Issue Date: February, 1998
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY100H607.PDF ] | |
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