|
|
PDF SY100H841 Data sheet ( Hoja de datos )
| Número de pieza | SY100H841 | |
| Descripción | SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SY100H841 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
SINGLE SUPPLY QUAD
PECL-TO-TTL W/LATCHED
OUTPUT ENABLE
ClockWorks™
SY10H841
SY100H841
FINAL
FEATURES
s Translates positive ECL to TTL (PECL-to-TTL)
s 300ps pin-to-pin skew
s 500ps part-to-part skew
s Differential internal design for increased noise
immunity and stable threshold inputs
s VBB reference output
s Single supply
s Enable input
s Latch enable input
s Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
s High drive capability: 24mA each output
s Fully compatible with industry standard 10K, 100K
I/O levels
s Available in 16-pin SOIC package
DESCRIPTION
The SY10/100H841 are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pull-
downs) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
BLOCK DIAGRAM
VBB
D
D
LEN
DQ
EN
PIN CONFIGURATION
LEN 1
16 Q3
Q0
EN 2
15 GT
GE 3
14 Q2
VE 4 SOIC 13 VT
Q1 D 5 Z16-1 12 VT
D6
11 Q1
VBB 7
10 GT
Q2
GT 8
9 Q0
Q3 PIN NAMES
Pin
GT
VT
VE
GE
D, D
VBB
Q0 - Q3
EN
LEN
Function
TTL Ground (0V)
TTL VCC (+5.0V)
ECL VCC (+5.0V)
ECL Ground (0V)
Signal Input (PECL)
VBB Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input
Rev.: F Amendment: /0
1 Issue Date: May, 1999
1 page  
Micrel
TTL SWITCHING CIRCUIT
USE 0.1µF CAPACITORS
FOR DECOUPLING.
PULSE
GENERATOR
50Ω COAX
VEE VCC & VCCO
PECL
TTL
IN DEVICE OUT
UNDER
TEST
450Ω
50Ω COAX
50Ω COAX
USE OSCILLOSCOPE
INTERNAL 50Ω LOAD
FOR TERMINATION.
CH A
CH B
OSCILLOSCOPE
ClockWorks™
SY10H841
SY100H841
ECL/TTL PROPAGATION DELAY — SINGLE ENDED
50%
VIN
Tpd++
VOUT
1.5V
Tpd– –
ECL/TTL WAVEFORMS: RISE AND FALL TIMES
VOUT
Trise
Tfall
2.0V
0.8V
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet SY100H841.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SY100H841 | SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE | Micrel Semiconductor |
| SY100H841L | 3.3V SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE | Micrel Semiconductor |
| SY100H842 | SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE | Micrel Semiconductor |
| SY100H842L | 3.3V SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE | Micrel Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |