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WM8152 데이터시트 PDF




Wolfson Microelectronics에서 제조한 전자 부품 WM8152은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 WM8152 기능
기능 Single Channel 16-bit CIS/CCD AFE
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WM8152 데이터시트, 핀배열, 회로
www.DataSheet4U.com
WM8152
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
The WM8152 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes a complete analogue signal processing
channel containing Reset Level Clamping, Correlated
Double Sampling, Programmable Gain and Offset adjust
functions. Internal multiplexers allow fast switching of offset
and gain for line-by-line colour processing. The output from
this channel is time multiplexed into a high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used to reference CIS signals or
during Reset Level Clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V, a digital core
voltage of 5V, and a digital interface supply of either 5V or
3.3V, the WM8152 typically only consumes 225mW when
operating from a single 5V supply.
BLOCK DIAGRAM
FEATURES
16-bit ADC
12MSPS conversion rate
Low power - 225mW typical
5V single supply or 5V/3.3V dual supply operation
Single channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
20-pin SSOP package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
VSMP MCLK
AVDD DVDD1 DVDD2
VRT VRX VRB
CL RS VS TIMING CONTROL
VREF/BIAS
VINP
VRLC/VBIAS
RLC
CDS
RLC 4
DAC
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
RM
GU
X
8
OFFSET
DAC
B
RM
GU
X
B
+ PGA
I/P SIGNAL
8 POLARITY
ADJUST
+
W
WM8152
16-
BIT
ADC
DATA
I/O
PORT
OP[0]
OP[1]
OP[2]
OP[3]/SDO
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
SEN
SCK
SDI
AGND1
AGND2
DGND
Production Data, January 2004, Rev 4.0
Copyright 2004 Wolfson Microelectronics plc




WM8152 pdf, 반도체, 판매, 대치품
WM8152
Production Data
PIN DESCRIPTION
PIN NAME
TYPE
DESCRIPTION
1 AGND2
Supply
Analogue ground (0V).
2 DVDD1
Supply
Digital core (logic and clock generator) supply (5V)
3
VSMP
Digital input Video sample synchronisation pulse.
4
MCLK
Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
5 DGND
Supply
Digital ground (0V).
6
SEN
Digital input Enables the serial interface when high.
7 DVDD2
Supply
Digital supply (5V/3.3V), all digital I/O pins.
8 SDI Digital input Serial data input.
9
SCK
Digital input Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below.
A BC
D
10
OP[0]
Digital output
d12
d8
d4
d0
11
OP[1]
Digital output
d13
d9
d5
d1
12
OP[2]
Digital output
d14
d10
d6
d2
13 OP[3]/SDO Digital output
d15
d11
d7
d3
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
14 AVDD
Supply
Analogue supply (5V)
15 AGND1
Supply
Analogue ground (0V).
16
VRB
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
17
VRT
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
18
VRX
Analogue output Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
19 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
20
VINP
Analogue input Video input.
w
PD Rev 4.0 January 2004
4

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WM8152 전자부품, 판매, 대치품
Production Data
WM8152
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP MAX
Programmable Gain Amplifier
Resolution
Gain equation
8
0.78 + PGA[7 : 0] × 7.57
255
Max gain
Min gain
Gain error
GMAX
GMIN
6.8 8.35 8.7
0.75 0.78 0.82
12
Internal channel offset
Analogue to Digital Converter
VOFF
10
Resolution
16
Maximum Speed
12
Full-scale input range
(2*(VRT-VRB))
VFS
2.5
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
VIH
VIL
IIH
IIL
CI
0.7 DVDD2
0.2 DVDD2
1
1
5
High level output voltage
VOH
IOH = 1mA
DVDD2 - 0.5
Low level output voltage
VOL IOL = 1mA
Supply Currents
0.5
Total supply current active
45
Total analogue AVDD, supply
current active
IAVDD
41
Total digital core, DVDD1,
supply current active
IDVDD1
3
Digital I/O supply current,
DVDD2 active (see note 3)
Supply current full power down
mode
IDVDD2
3
300 400
Notes:
3. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is
measured with approximately 50pF attached to the pin.
UNIT
bits
V/V
V/V
V/V
%
mV
bits
MSPS
V
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
µA
w
PD Rev 4.0 January 2004
7

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