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PDF 56F8037 Data sheet ( Hoja de datos )
| Número de pieza | 56F8037 | |
| Descripción | 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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56F8037
Data Sheet
Preliminary Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8037
Rev. 2
12/2006
freescale.com
1 page  
56F8037 Features
Part 1 Overview
1.1 56F8037 Features
1.1.1 Digital Signal Controller Core
• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2 Memory
• Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
• On-chip memory
— 64KB of Program Flash
— 8KB of Unified Data/Program RAM
• EEPROM emulation capability using Flash
1.1.3 Peripheral Circuits for 56F8037
• One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and Edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
Freescale Semiconductor
Preliminary
56F8037 Data Sheet, Rev. 2
5
5 Page 
Architecture Block Diagram
To/From IPBus Bridge
IPBus
INTC
SYNC
PIT0
MSTR_CNT_EN
MSTR_CNT_EN SYNC
PIT1
3
DAC SYNC on Figure 1-5
MSTR_CNT_EN SYNC
PIT2
2 SYNC0, SYNC1 on Figure 1-7
3 LIMIT on Figure 1-6
Sync0,
Sync1
Over/Under
Limits
ANA0
ANA2 (VREFHA)
ANA3 (VREFLA)
ANA4
ANA1, 5-7
ANA0 on Figure 1-5
ANA4 on Figure 1-4
ANA1, 5-7
4
ADC
ANB0
ANB2 (VREFHA)
ANB3 (VREFLB)
ANB4
ANB1, 5-7
ANB0 on Figure 1-5
ANB4 on Figure 1-4
ANB1, 5-7
4
GPIOC2
GPIOC3
GPIOC1, 9-11
GPIOC6
GPIOC7
GPIOC5, 13-15
Figure 1-3 56F8037 I/O Pin-Out Muxing (Part 1/5)
Freescale Semiconductor
Preliminary
56F8037 Data Sheet, Rev. 2
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 56F8037.PDF ] | |
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