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ZL30410 데이터시트 PDF




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부품번호 ZL30410 기능
기능 Multi-service Line Card PLL
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ZL30410 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ZL30410
Multi-service Line Card PLL
Data Sheet
Features
• Generates clocks for OC-3, STM-1, DS3, E3,
DS2, DS1, E1, 19.44 MHz and ST-BUS
• Meets jitter generation requirements for STM-1,
OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces
• Compatible with GR-253-CORE SONET stratum
3 and G.813 SEC timing compliant clocks
• Provides “hit-less” reference switching
• Detects frequency of both reference clocks and
synchronizes to any combination of 8 kHz, 1.544
MHz, 2.048 MHz and 19.44 MHz reference
frequencies
• Continuously monitors both references for
frequency accuracy exceeding ±12 ppm
• Holdover accuracy of 70x10 -12 meets GR-1244
Stratum 3E and ITU-T G.812 requirements
• Meets requirements of G.813 Option 1 for SDH
Equipment Clocks (SEC) and GR-1244 for
Stratum 4E and Stratum 4 Clocks
• 3.3V power supply
Applications
• Line Card synchronization for SDH, SONET, DS3,
E3, J2 (DS2), E1 and DS1 interfaces
• Timing card synchronization for SDH and PDH
Network Elements
November 2003
Ordering Information
ZL30410QCC
80 Pin LQFP
-40°C to 85°C
• Clock generation for ST-BUS and GCI timing
Description
The ZL30410 is a Multi-service Line Card
Phase-Locked Loop designed to generate multiple
clocks for SONET, SDH and PDH equipment including
timing for ST-BUS and GCI interfaces.
The ZL30410 operates in NORMAL (LOCKED),
HOLDOVER and FREE-RUN modes to ensure that in
the presence of jitter and interruptions to the reference
signals, the generated clocks meet international
standards. The filtering characteristics of the PLL are
hardware pin selectable and they do not require any
external adjustable components. The ZL30410 uses an
external 20 MHz Master Clock Oscillator to provide a
stable timing source for the HOLDOVER operation.
PRI
PRIOR
SEC
SECOR
RefSel
RESET
VDD GND
Primary
Acquisition
PLL
Secondary
Acquisition
PLL
C20i
Master Clock
Frequency
Calibration
MUX
FCS
Core PLL
OE
APLL
Clock
Synthesizer
Control State Machine
JTAG
IEEE
1149.1a
MS1 MS2 RefAlign LOCK HOLDOVER
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
C155P/N
C34/C44
C19o
C16o
C8o
C6o
C4o
C2o
C1.5o
F16o
F8o
F0o
E3DS3/OC3
E3/DS3
Tclk
Tdi
Tdo
Tms
Trst
07




ZL30410 pdf, 반도체, 판매, 대치품
Pin Description
Pin #
1
2-5
6
7, 8
9
Name
IC
NC
GND
NC
FCS
10 VDD
11 GND
12 F16o
13 C16o
14 C8o
15 C4o
16 C2o
17 F0o
18 MS1
19 MS2
20 F8o
ZL30410
Data Sheet
.
Description
Internal Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Ground. Negative power supply.
No internal bonding Connection. Leave unconnected.
Filter Characteristic Select (Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
Positive Power Supply.
Ground.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS tristate output). This is an 8 kHz,
61ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS tristate output). This is an 8 kHz,
244ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096
Mb/s.
Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mb/s. See Figure 15 for details.
4
Zarlink Semiconductor Inc.

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ZL30410 전자부품, 판매, 대치품
ZL30410
Data Sheet
Pin Description (continued)
Pin #
Name
53 C34/C44
54 VDD
55 HOLDOVER
56 NC
57 LOCK
58 NC
59 IC
60 IC
61 SECOR
62 OE
63 NC
64 RESET
65
66-69
70
71, 72
73
74 - 77
78, 79
80
NC
IC
GND
IC
VDD
IC
NC
IC
Description
Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is
programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz
(for DS3 applications) when E3DS3/OC3 is high, or to be either 8.592 MHz or
11.184 MHz when E3DS3/OC3 is low. See description of E3DS3/OC3 and
E3/DS3 inputs for details.
Positive Power Supply.
Holdover Indicator (CMOS output). Logic high at this output indicates that the
device is in Holdover mode.
No internal bonding Connection. Leave unconnected.
Lock Indicator (CMOS output). Logic high at this output indicates that
ZL30410 is locked to the input reference. See LOCK indicator description in
Section 2.2.3, “Lock Indicator (LOCK),” on page 9.
No internal bonding Connection. Leave unconnected.
Internal Connection. Connect to logic high.
Internal Connection. Connect to ground.
Secondary Reference Out of Range (Output). Logic high at this pin indicates
that the Secondary Reference is off the PLL centre frequency by more than
±12ppm. See SECOR (PRIOR) pin description in Section 3.2 on page 15 for
details.
Output Enable (Input). Logic high on this input enables C19, F16, C16, C8,
C6, C4, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output
clocks pins into a high impedance state.
No internal bonding Connection. Leave unconnected.
RESET (5V tolerant input). The ZL30410 must be reset after power-up in order
to set internal functional blocks into a default state. The internal reset is
performed by forcing RESET pin low for a minimum of 1 µs after the C20
Master Clock is applied to pin C20i. This operation forces the ZL30410 internal
state machine into a RESET state for a duration of 625 µs.
No internal bonding Connection. Leave unconnected.
Internal connection. Connect these pins to logic high.
Ground.
Internal Connection (Input). Connect these pins to ground.
Positive Power Supply.
Internal connection. Connect these pins to logic high.
No internal bonding Connection. Leave unconnected.
Internal Connection (Input). Connect this pin to ground.
7
Zarlink Semiconductor Inc.

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