PDF ZL30415 Data sheet ( Hoja de datos )

Número de pieza	ZL30415
Descripción	SONET/SDH Clock Multiplier PLL
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ZL30415 SONET/SDH Clock Multiplier PLL Data Sheet Features • Meets jitter requirements of Telcordia GR-253- CORE for OC-12, OC-3, and OC-1 rates • Meets jitter requirements of ITU-T G.813 for STM- 4, and STM-1 rates • Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz • Provides a single-ended CMOS output clock at 19.44 MHz • Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL, or CML reference at 19.44 MHz or 77.76 MHz • Provides a LOCK indication • 3.3 V supply Applications • SONET/SDH line cards November 2004 Ordering Information ZL30415GGC 64 Ball CABGA -40°C to +85°C Description The ZL30415 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30415 generates low jitter output clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-4 and STM-1 rates. The ZL30415 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDS, LVPECL, or CML reference at 19.44 MHz or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or 622.08 MHz, and a single-ended CMOS clock at 19.44 MHz. The ZL30415 provides a lock indication. REF_SEL LPF FS3 FS2 FS1 C19i REFinP/N C19i or C77i CML, LVDS, LVPECL input Reference Selection MUX Frequency & Phase Detector State Machine Loop Filter VCO 19.44 MHz and 77.76 MHz Reference and Bias Circuit Frequency Dividers and Clock Drivers REF_FREQ LOCK BIAS VCC GND VDD C19oEN C19o, C38o, C77o, C155o, C622o, LVPECL output OC-CLKoP/N C19o 03 Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30415 Data Sheet 2.2 Frequency/Phase Detector The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit. 2.3 Lock Indicator The ZL30415 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm. 2.4 Loop Filter The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF ball and ground as shown in Figure 3. Frequency and Phase Detector VCO ZL30415 Loop Filter LPF RF CF RF=8.2 kΩ, CF=470 nF Figure 3 - Loop Filter Elements 2.5 VCO The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks. 5 Zarlink Semiconductor Inc. 5 Page ZL30415 Data Sheet 4.2.2 Interfacing to OC-CLKo Output 4.2.2.1 LVPECL to LVPECL Interface The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and 19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed close to the LVPECL receiver. +3.3 V Typical resistor values: R1 = 127Ω, R2 =82.5Ω ZL30415 VCC 0.1uF LVPECL Driver OC-CLKoP OC-CLKoN GND Z=50Ω Z=50Ω VCC=+3.3 V R1 R1 LVPECL Receiver R2 R2 Figure 9 - LVPECL to LVPECL Interface 11 Zarlink Semiconductor Inc. 11 Page

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