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ZL30416 데이터시트 PDF




Zarlink Semiconductor에서 제조한 전자 부품 ZL30416은 전자 산업 및 응용 분야에서
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부품번호 ZL30416 기능
기능 SONET/SDH Clock Multiplier PLL
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ZL30416 데이터시트, 핀배열, 회로
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ZL30416
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
• Low jitter clock outputs suitable for OC-192, OC-
48, OC-12, OC-3 and OC-1 SONET applications
as defined in Telcordia GR-253-CORE
• Low jitter clock outputs suitable for STM-64, STM-
16, STM-4 and STM-1 applications as defined in
ITU-T G.813
• Provides one differential LVPECL output clock
selectable to 19.44, 38.88, 77.76, 155.52 or
622.08 MHz
• Provides a single-ended CMOS output clock at
19.44 MHz
• Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL or
CML reference at 19.44 or 77.76 MHz
• Provides a LOCK indication
• 8 mm x 8 mm CABGA package
• 3.3 V supply
Applications
• SONET/SDH line cards
November 2004
Ordering Information
ZL30416GGG
64 Ball CABGA
-40°C to +85°C
Description
The ZL30416 is an Analog Phase-Locked Loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30416 generates low
jitter output clocks suitable for Telcordia GR-253-
CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and
ITU-T G.813 STM-64, STM-16, STM-4 and STM-1
applications.
The ZL30416 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL or CML
reference at 19.44 or 77.76 MHz and generates a
differential LVPECL output clock selectable to 19.44,
38.88, 77.76, 155.52 or 622.08 MHz and a single-
ended CMOS clock at 19.44 MHz. The ZL30416
provides a lock indication.
REF_SEL
LPF
FS3 FS2 FS1
C19i
REFinP/N
C19i or C77i
CML, LVDS,
LVPECL input
Reference
Selection
MUX
Frequency
& Phase
Detector
State
Machine
Loop
Filter
VCO
19.44 MHz and 77.76 MHz
Reference
and
Bias Circuit
Frequency
Dividers
and
Clock
Drivers
REF_FREQ LOCK
BIAS
VCC GND VDD C19oEN
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
OC-CLKoP/N
C19o
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.




ZL30416 pdf, 반도체, 판매, 대치품
ZL30416
Data Sheet
Ball Description Table (continued)
Ball #
F6
F7, G1
G2
G3
G4
G5, G6
G7, G8
H1, H2
H3
H4
H5
H6
H7, H8
Name
C19o
GND
VDD
REF_SEL
FS3
GND
VDD
NC
VDD
FS1
VDD
GND
Description
Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS
clock at 19.44 MHz.
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
Reference Select (CMOS Input). If tied low then the C19i single-ended
reference is used as the input reference source. If tied high then the REFinP/N
differential pair is used as the input reference source.
See E4 ball description.
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
No internal bonding Connection. Leave unconnected.
Positive Digital Power Supply. +3.3 V ±10%
See E4 ball description.
Positive Digital Power Supply. +3.3 V ±10%
Ground. 0 volt.
2.0 Functional Description
The ZL30416 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block
diagram of the ZL30416 is shown in Figure 1 and a brief description is presented in the following sections.
2.1 Reference Selection Multiplexer
The ZL30416 accepts two types of input reference clocks:
- differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels
- single-ended: operating at 19.44 MHz, compatible with CMOS switching levels
The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential
reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the
differential input clock to be either 19.44 MHz or 77.76 MHz. See Table 1 for details.
REF_SEL
0
1
1
REF_FREQ Selected Input Reference
Reference Frequency
x
C19i
19.44 MHz (CMOS)
0
REFin
77.76 MHz (Differential)
1
REFin
19.44 MHz (Differential)
Table 1 - Input Reference Selection
4
Zarlink Semiconductor Inc.

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ZL30416 전자부품, 판매, 대치품
ZL30416
Data Sheet
3.0 ZL30416 Performance
The following are some of the ZL30416 performance indicators that complement results listed in the Characteristics
section of this data sheet.
3.1 Input Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) in the presence of jitter applied to its input
reference. The input jitter tolerance of the ZL30416 is shown in Figure 4. On this graph, the single line at the top
represents the input jitter tolerance and the three overlapping lines below represent the specification for minimum
input jitter tolerance for OC-192, OC-48 and OC-12 network interfaces. The jitter tolerance is expressed in
picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
3.2 Jitter Transfer Characteristic
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a
PLL. This ratio is expressed in dB and it characterizes the PLL’s ability to attenuate (filter) jitter. The ZL30416 jitter
transfer characteristic complies with the maximum 0.1 dB jitter gain specified in Telcordia’s GR-253-CORE.
7
Zarlink Semiconductor Inc.

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