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PE9763 데이터시트 PDF




Peregrine Semiconductor에서 제조한 전자 부품 PE9763은 전자 산업 및 응용 분야에서
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부품번호 PE9763 기능
기능 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer
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PE9763 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Product Description
Peregrine’s PE9763 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE9763 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, a phase comparator and a
charge pump as shown in Figure 1. Counter values are
programmable through either a serial interface or directly hard-
wired.
PE9763 is optimized for commercial space applications. Single
Event Latch up (SEL) is physically impossible and Single Event
Upset (SEU) is better than 10-9 errors per bit / day. Fabricated
in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS
technology, the PE9763 offers excellent RF performance and
intrinsic radiation tolerance.
Product Specification
PE9763
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
3.2 GHz operation
÷10/11 dual modulus prescaler
Selectable phase detector or charge
pump output
Serial or Direct mode access
Frequency selectivity: Comparison
frequency / 218
Low power —- 25 - 30 mA at 3V (phase
detector / charge pump)
Rad-Hard
Ultra-low phase noise
68-lead CQFJ or Die
Figure 1. Block Diagram
Fin
Fin
M8:0
A3:0
R5:0
Pre_en
20
Sdata
Primary
21-bit
Latch
fr
K17:0
Direct
Prescaler
10/11
Secon-
dary
20-bit
Latch
Auxilia-
ry
20-bit
Latch
18
20
18
2
Main
Counter
13
+
19
4
DSM
13
66
R Counter
Phase
Detector
PD_U
PD_D
Charge
Pump
CP
Document No. 70-0140-01 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15




PE9763 pdf, 반도체, 판매, 대치품
PE9763
Product Specification
Pin No.
46
47
Pin
Name
VDD
VDD
Fin
Valid
Mode
Both
Type
(Note 1)
(Note 1)
Input
Description
ESD VDD.
Prescaler VDD.
Prescaler input from the VCO. 3.2 GHz max frequency.
48 Fin
GND
Both
Input
Downbond
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 W resistor directly to the ground plane.
Prescaler ground.
49 GND
Downbond Prescaler ground.
GND
50 CEXT
51 LD
52 DOUT
Both
Both
Both
Downbond
Output
Output
Output
Output driver/charge pump ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kW series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
53 VDD
(Note 1)
Output driver/charge pump VDD.
54 GND
55 PD_D
56 CP
57 PD_U
Both
Both
Both
Downbond
Output
Output
Output
Output driver/charge pump ground.
PD_D pulses down when fp leads fc. PD_U is driven to GND when CPSEL = “High”.
Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”.
PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”.
58 GND
Downbond Output driver/charge pump ground.
59 VDD
(Note 1)
Output driver/charge pump VDD.
GND
Downbond Phase detector GND.
VDD
60
VDD
(Note 1)
(Note 1)
Phase detector VDD.
ESD VDD.
GND
61
GND
62 fr
Both
Downbond
Downbond
Input
ESD ground.
Reference ground.
Reference frequency input.
63 VDD
(Note 1)
Reference VDD.
64 VDD
(Note 1)
Digital core VDD.
GND
Downbond Digital core ground.
65 ENH
Both
66 CPSEL Both
67 MS2_SEL Both
Input
Input
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by
forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D.
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68
Note 1:
Note 2:
RND_SEL Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 219.
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kpull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0140-01 UltraCMOS™ RFIC Solutions

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PE9763 전자부품, 판매, 대치품
PE9763
Product Specification
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
tCWR
tCE
tWRC
tEC
Fin
PFin
Fin
PFin
fr
Pfr
fc
ΦN
ΦN
Parameter
Conditions
Min Typ Max
Control Interface and Latches (see Figures 3, 4)
Serial data clock frequency
(Note 1)
10
Serial clock HIGH time
30
Serial clock LOW time
30
Sdata set-up time to Sclk rising edge
10
Sdata hold time after Sclk rising edge
10
S_WR pulse width
30
Sclk rising edge to S_WR rising edge
30
Sclk falling edge to E_WR transition
30
S_WR falling edge to Sclk rising edge
30
E_WR transition to Sclk rising edge
30
Main Divider (Including Prescaler) (Note 4)
Operating frequency
275 3200
Input level range
External AC coupling
-5
5
Main Divider (Prescaler Bypassed) (Note 4)
Operating frequency
50 300
Input level range
External AC coupling
-5
5
Reference Divider
Operating frequency
(Note 3)
100
Reference input power (Note 2)
Single ended input
-2
Phase Detector
Comparison frequency
(Note 3)
50
SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 10 MHz, LBW = 50 kHz, VDD = 3.0 V, Temp = 25° C) (Note 4)
Phase Noise
1 kHz Offset
-88
Phase Noise
10 kHz Offset
-92
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
MHz
dBm
MHz
dBm
MHz
dBc/Hz
dBc/Hz
Note 1:
Note 2:
Note 3:
Note 4:
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.
Document No. 70-0140-01 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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