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ISL12026 데이터시트 PDF




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부품번호 ISL12026 기능
기능 Real Time Clock/Calendar
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ISL12026 데이터시트, 핀배열, 회로
®
Data Sheet
ISL12026, ISL12026A
November 30, 2010
FN8231.9
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12026 and the ISL12026A devices are micro power
real time clocks with timing and crystal compensation,
clock/calender, power-fail indicator, two periodic or polled
alarms, intelligent battery backup switching, and integrated
512x8-bit EEPROM configured in 16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12026 and ISL12026A have different types of Power
Control Settings. The ISL12026 uses the Legacy Mode
Setting, which follows conditions set in X1226 products. The
ISL12026A uses the Standard Mode Setting. Please refer to
“Power Control Operation” on page 13 for more details. Also,
please refer to “I2C Communications During Battery Backup”
on page 22 for important details.
Pinouts
ISL12026, ISL12026A
(8 LD SOIC)
TOP VIEW
X1
X2
IRQ/FOUT
GND
1
2
3
4
8 VDD
7 VBAT
6 SCL
5 SDA
ISL12026, ISL12026A
(8 LD TSSOP)
TOP VIEW
VBAT
VDD
X1
X2
1
2
3
4
8 SCL
7 SDA
6 GND
5 IRQ/FOUT
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2006, 2007, 2008, 2010. All Rights Reserved.
Intersil (and design) and BlockLock are trademarks owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.




ISL12026 pdf, 반도체, 판매, 대치품
ISL12026, ISL12026A
EEPROM Specifications
PARAMETER
EEPROM Endurance
EEPROM Retention
TEST CONDITIONS
Temperature ≤ +75°C
MIN
(Note 16)
>2,000,000
50
TYP
MAX
(Note 16)
UNITS
Cycles
Years
NOTES
Serial Interface (I2C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
VIL SDA and SCL Input Buffer LOW
Voltage
VIH SDA and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer
Hysteresis
VOL SDA Output Buffer LOW Voltage
ILI Input Leakage Current on SCL
ILO I/O Leakage Current on SDA
TEST CONDITIONS
IOL = 4mA
VIN = 5.5V
VIN = 5.5V
MIN
(Note 16)
-0.3
TYP
MAX
(Note 16)
0.3xVDD
UNITS
V
NOTES
0.7 x VDD
VDD + 0.3
V
0.05 x VDD
V
0 0.4
100
100
V
nA
nA
AC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
fSCL SCL Frequency
tIN Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed.
tAA
tBUF
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to 70%
of VDD window.
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing
70% of VDD during the following
START condition.
tLOW Clock LOW Time
Measured at the 30% of VDD
crossing.
tHIGH Clock HIGH Time
Measured at the 70% of VDD
crossing.
tSU:STA START Condition Set-up Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Set-up Time
tHD:DAT Input Data Hold Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD.
From SCL rising edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
MIN
(Note 16)
1300
1300
600
600
600
100
0
TYP
MAX
(Note 16) UNITS
400 kHz
50 ns
NOTES
900 ns
ns
ns
ns
ns
ns
ns
ns
4 FN8231.9
November 30, 2010

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ISL12026 전자부품, 판매, 대치품
ISL12026, ISL12026A
Typical Performance Curves (Continued)Temperature is +25°C unless otherwise specified.
4.5 80
4.0
60
3.5
3.0 40
2.5
20
2.0
1.5 0
1.0
-20
0.5
0.0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VDD (V)
-40
-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28
ATR SETTING
FIGURE 5. IDD3 vs VDD
FIGURE 6. ΔFOUT vs ATR SETTING
Description
The ISL12026 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8 EEPROM,
oscillator compensation and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real Time Clock keeps track of time with separate
registers for Hours, Minutes and Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
The Dual Alarms can be set to any Clock/Calendar value for
a match. For instance, every minute, every Tuesday, or 5:23
AM on March 21. The alarms can be polled in the Status
Register or can provide a hardware interrupt (IRQ/FOUT
Pin). There is a pulse mode for the alarms allowing for
repetitive alarm functionality.
The IRQ/FOUT pin may be software selected to provide a
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The device offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or SuperCap.
The entire ISL12026 device is fully operational from 2.7V to
5.5V and the clock/calendar portion of the ISL12026 device
remains fully operational down to 1.8V (Standby Mode).
The ISL12026 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock™ allows a
safe, secure memory for critical user and configuration data,
while allowing a large user storage area.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
gated). The pull-up resistor on this pin must use the same
voltage source as VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as VDD. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-down. The
circuit is designed to comply with 400kHz I2C interface speed.
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event the VDD
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/FOUT mode is selected via
the frequency out control bits of the INT register.
Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is
an open drain output.
7 FN8231.9
November 30, 2010

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