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ISL12027 데이터시트 PDF




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기능 Real Time Clock/Calendar
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ISL12027 데이터시트, 핀배열, 회로
®
Data Sheet
ISL12027, ISL12027A
August 12, 2010
FN8232.8
Real Time Clock/Calendar with EEPROM
The ISL12027 device is a low power real time clock with
timing and crystal compensation, clock/calender, power-fail
indicator, two periodic or polled alarms, intelligent battery
backup switching, CPU Supervisor and integrated 512x8-bit
EEPROM, in 16 Byte per page format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12027 and ISL12027A Power Control Settings are
different. The ISL12027 uses the Legacy Mode Setting, and
the ISL12027A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12027A. Please refer to“Power Control Operation” on
page 15 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 24 for important details.
Pinouts
ISL12027, ISL12027A
(8 LD TSSOP)
TOP VIEW
VBAT
VDD
X1
X2
1
2
3
4
8 SCL
7 SDA
6 GND
5 RESET
ISL12027, ISL12027A
(8 LD SOIC)
TOP VIEW
X1
X2
RESET
GND
1
2
3
4
8 VDD
7 VBAT
6 SCL
5 SDA
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8-Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I2C-bus™ Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C-bus™ is a trademark of NXP B.V., BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries
Copyright Intersil Americas Inc. 2005, 2006, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




ISL12027 pdf, 반도체, 판매, 대치품
ISL12027, ISL12027A
Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, and RESET pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (Notes 5, 6) . . . . . 115
50
8 Ld TSSOP Package (Notes 5, 6) . . .
140
40
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
DC Electrical Specifications Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C and
VDD = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
MAX
(Note 16)
UNIT
NOTES
VDD
VBAT
Main Power Supply
Backup Power Supply
2.7 5.5 V
1.8 5.5 V
Electrical Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
IDD1 Supply Current with I2C Active
IDD2
IDD3
IBAT
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
IBATLKG Battery Input Leakage
VTRIP VBAT Mode Threshold
VTRIPHYS VTRIP Hysteresis
VBATHYS VBAT Hysteresis
VDD SR- VDD Negative Slew rate
RESET OUTPUT
CONDITIONS
VDD = 2.7V
VDD = 5.5V
VDD = 2.7V
VDD = 5.5V
VDD = VSDA = VSCL = 2.7V
VDD = VSDA = VSCL = 5.5V
VBAT = 1.8V,
VDD = VSDA = VSCL= VRESET = 0V
VBAT = 3.0V,
VDD = VSDA = VSCL= VRESET = 0V
VDD = 5.5V, VBAT = 1.8V
MIN
(Note 16)
-100
1.8
TYP
800
850
2.2
30
50
MAX
(Note 16)
500
800
2.5
3.5
10
20
1000
1200
100
2.6
10
VOL Output Low Voltage
ILO Output Leakage Current
VDD = 5.5V
IOL = 3mA
VDD = 2.7V
IOL = 1mA
VDD = 5.5V
VOUT = 5.5V
0.4
0.4
100 400
UNIT
µA
µA
mA
mA
µA
µA
nA
NOTES
7, 8, 9
7, 8, 9
9
7, 10, 11
nA
nA
V
mV
mV
V/ms
11
11, 14
11, 14
12
V
V
nA
4 FN8232.8
August 12, 2010

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ISL12027 전자부품, 판매, 대치품
Timing Diagrams
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
ISL12027, ISL12027A
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA tDH
FIGURE 1. BUS TIMING
tHD:STO
tSU:STO
tBUF
SCL
SDA
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
FIGURE 2. WRITE CYCLE TIMING
tWC
START
CONDITION
SCL
SDA
tRSP
tRSP<tWDO
tRSP>tWDO
tRST
tRSP>tWDO
tRST
RESET
START
STOP START
Note: All inputs are ignored during the active reset period (tRST).
FIGURE 3. WATCHDOG TIMING
VDD
VRESET
tPURST
RESET
tR
7
tRPD
tPURST
FIGURE 4. RESET TIMING
tF
VRVALID
FN8232.8
August 12, 2010

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