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부품번호 A8499 기능
기능 High Voltage Step-Down Regulator
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A8499 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features and Benefits
8 to 50 V input range
Integrated DMOS switch
Adjustable fixed off-time
Highly efficient
Adjustable 1.2 to 24 V output
A8499
High Voltage Step-Down Regulator
Description
The A8499 is a step down regulator that will handle a wide
input operating voltage range.
The A8499 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ).
Applications include:
Printer power supplies
Consumer equipment power supplies
Package: 8-Lead SOIC with exposed
thermal pad (suffix LJ)
Approximate Scale 1:1
Typical Application
CBOOT
0.01 μF
BOOT
VIN
ENB
RTSET
121 kΩ
TSET
GND
A8499
LX
VBIAS
FB
D1
+42 V
C3
100 μF
50 V
C3
0.22 μF
L1
47 μH
R1
17.8 kΩ
R2
10.2 kΩ
VOUT
3.3 V / 1.2 A
ESR
COUT
220 μF
10 V
90.0
88.0
86.0
84.0
82.0
80.0
78.0
76.0
74.0
72.0
70.0
0
Efficiency vs. Output Current
VOUT (V)
3.3
5
200 400 600 800 1000 1200 1400
IOUT (mA)
Circuit for 42 V step down to 3.3 V at 1.2 A. Efficiency data from circuit shown in left panel.Data is for reference only.
A8499-DS, Rev. 3




A8499 pdf, 반도체, 판매, 대치품
A8499
High Voltage Step-Down Regulator
Functional Description
The A8499 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continu-
ous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time (see graph in the toff section).
VOUT. The output voltage is adjustable from 1.2 to 24 V, based on
the combination of the value of the external resistor divider and
the internal 1.2 V ±3% reference. The voltage can be calculated
with the following formula:
VOUT = VFB × (1 + R1/R2)
(1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skip-
ping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the out-
put to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 2.2 A minimum.
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
VBIAS. To improve overall system efficiency, the regulator output,
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During start up
the circuitry is run off of the VIN supply. VBIAS should be con-
nected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A8499 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal opperation.
ON/OFF Control. The ENB pin is externally pulled to ground
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF. The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (μs)
is:
tOFF
=
RTSET
1.2 1010
,
(2)
where RTSET (kΩ) is the value of the resistor. Results are shown
in the following graph:
Resistance vs. Off-Time
17
15
13
11
9
7
5
3
1
12 36 60 84 108 132 156 180
RTSET (kΩ)
tON. From the volt-second balance of the inductor, the turn-on
time, tON , can be calculated approximately by the equation:
tON =
(VOUT + Vf + IOUT RL) tOFF
VIN IOUT RDS(on) IOUT RL VOUT
(3)
where
Vf is the voltage drop across the external Schottky diode,
RL is the winding resistance of the inductor, and
RDS(on) is the on-resistance of the switching MOSFET.
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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A8499 전자부품, 판매, 대치품
A8499
High Voltage Step-Down Regulator
Package LJ 8-Pin SOIC
5.00 .197
8 4.80 .189
B
A
6.20 .244
5.80 .228
0.25 [.010] M B M
A
B
4.00 .157
3.80 .150
2.41 .095
NOM
0.25 .010
0.17 .007
1.27 .050
0.40 .016
12
3.30 .130
NOM
8X
0.10 [.004] C
8X
0.51
0.31
.020
.012
0.25 [.010] M C A B
1.27 .050
SEATING C
PLANE
1.75 .069
1.35 .053
0.25 .010
0.10 .004
0.25 .010
SEATING PLANE
GAUGE PLANE
0.65 .026
MAX
1.27 .050
NOM
1.75 .069
NOM
2X 0.20 .008
MIN
C
3.30 .130
NOM
1
2
2.41 .095
NOM
5.60 .220
NOM
6X 0.20 .008
MIN
All dimensions reference, not for tooling use
(reference JEDEC MS-012 AA)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
The products described herein are manufactured under one or more patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written ap-
proval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringements of patents or other rights of third parties that may result from its use.
Copyright © 2005, 2006 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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