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PDF 82C862 Data sheet ( Hoja de datos )
| Número de pieza | 82C862 | |
| Descripción | FireLink USB Dual Controller Quad Port USB | |
| Fabricantes | OPTi | |
| Logotipo |  |
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®
FireLink USB
82C862
Dual Controller
Quad Port USB
Preliminary Data Book
CONFIDENTIAL
912-2000-030
Revision 1.0
1 page  
®
1.0 Features
• Compliant with USB rev. 1.1 specification
• Fully compatible with USB OHCI specification
• Two independent host controllers, two ports each,
making FireLink USB a multi-function PCI device
• Second host controller can be disabled if not used
• Clock input can be derived from either a 12MHz crystal
or a 48MHz oscillator
• Clocks can be turned off when not in use to save power
• Core operates at 3.3V; PCI inputs are 5V-tolerant
• Incorporates PCI Power Management, supporting very
low power standby modes
Figure 1. 82C862 FireLink USB Block Diagram
FireLink USB
82C862
• Implements CLKRUN# pin to support hardware-
enforced power-down
• Packaged as 100-pin LQFP (Low-profile Quad Flat
Pack)
• Supported by Windows 98, Windows 2000, and
Windows CE
2.0 Overview
This document describes the OPTi FireLink USB (82C862)
controller.
This PCI-to-USB bridge is unique in that it consists of two
independent dual-port controllers, each sharing only the
common PCI bus connection. This arrangement allows for
a total Universal Serial Bus bandwidth of 24Mb/s, divided
into 12Mb/s for each pair of ports.
Figure 1 provides a block diagram of the overall
functionality of the chip.
FireLink USB
82C862
PCI
interface
R E Q #, GNT#
C e n tr a l
Arbiter
48MHz Clock
G e n e r a tio n
USB
Controller
M odule 1
U S B C o n fig
Regs Function 0
port 1
port 2
USB
Controller
M odule 2
U S B C o n fig
Regs Function 1
port 3
port 4
12MHz
xtal
912-2000-030
Revision: 1.0
Page 1
5 Page 
PAR
FRAME#
IRDY#
TRDY#
STOP#
FireLink USB
82C862
76 O Even Parity: The 82C862 calculates PAR for both the address and data phases
of PCI cycles. PAR is valid one PCI clock after the associated address or data
phase, but may or may not be valid for subsequent clocks. It is calculated based
on 36 bits - AD[31:0] plus C/BE[3:0]#. "Even" parity means that the sum of the 36
bit values plus PAR is always an even number, even if one or more bits of
C/BE[3:0]# indicate invalid data.
64 I/O Cycle Frame: This signal is driven by the current PCI bus master to indicate the
(s/t/s) beginning and duration of an access. The master asserts FRAME# at the
beginning of a bus cycle, sustains the assertion during data transfers, and then
negates FRAME# in the final data phase.
FRAME# is an input when the 82C862 is the target and an output when it is the
initiator.
FRAME# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or slave by the 82C862.
67 I/O Initiator Ready: IRDY#, along with TRDY#, indicates whether the 82C862 is able
(s/t/s) to complete the current data phase of the cycle. IRDY# and TRDY# are both
asserted when a data phase is completed.
During a write, the 82C862 asserts IRDY# to indicate that it has valid data on
AD[31:0]. During a read, the 82C862 asserts IRDY# to indicate that it is prepared
to accept data.
IRDY# is an input when the 82C862 is a target and an output when it is the
initiator.
IRDY# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or a slave by the 82C862.
68 I/O Target Ready: TRDY#, along with IRDY#, indicates whether the 82C862 is able
(s/t/s) to complete the current data phase of the cycle. TRDY# and IRDY# are both
asserted when a data phase is completed.
When the 82C862 is acting as the target during read and write cycles, it performs
in the following manner:
1. During a read, the 82C862 asserts TRDY# to indicate that it has placed valid
data on AD[31:0].
2. During a write, the 82C862 asserts TRDY# to indicate that is prepared to
accept data.
TRDY# is an input when the 82C862 is the initiator and an output when it is the
target.
TRDY# is tristated from the leading edge of RESET# and remains so until driven
as either a master or a slave by the 82C862.
70 I/O Stop: STOP# is an output when the 82C862 is the target and an input when it is
(s/t/s) the initiator. As the target, the 82C862 asserts STOP# to request that the master
stop the current cycle. As the master, the assertion of STOP# by a target forces
the 82C862 to stop the current cycle.
STOP# is tristated from the leading edge of RESET# and remains so until driven
by the 82C862 acting as a slave.
912-2000-030
Revision 1.0
®
Page 7
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82C862.PDF ] | |
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