TC55NEM208AFPN Datasheet PDF - Toshiba Semiconductor
| Part Number | TC55NEM208AFPN | |
| Description | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS | |
| Manufacturers | Toshiba Semiconductor | |
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TC55NEM208AFPN/AFTN55,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5V ± 10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA
standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select
the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of −40° to 85°C, the TC55NEM208AFPN/AFTN can be used in
environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a
standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
• Low-power dissipation
Operating: 15 mW/MHz (typical)
• Single power supply voltage of 5 V ± 10%
• Power down features using CE .
• Data retention supply voltage of 2.0 to 5.5 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum):20 µA
• Access Times (maximum):
TC55NEM208AFPN/AFTN
55 70
Access Time
55 ns
70 ns
CE Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
• Package:
SOP32-P-525-1.27 (AFPN)
(Weight:
TSOP II32-P-400-1.27 (AFTN) (Weight:
g typ)
g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN SOP & TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VDD
31 A15
30 A17
29 R/W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
(AFPN/AFTN)
PIN NAMES
A0~A18
R/W
OE
CE
I/O1~I/O8
VDD
GND
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power (+5 V)
Ground
2002-09-18 1/10
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TIMING DIAGRAMS
READ CYCLE (See Note 1)
Address
A0~A18
CE
OE
DOUT
I/O1~8
Hi-Z
TC55NEM208AFPN/AFTN55,70
tRC
tACC
tCO
tOE
tOH
tOD
tOEE
tCOE
tODO
VALID DATA OUT
Hi-Z
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
Address
A0~A18
R/W
CE
DOUT
I/O1~8
DIN
I/O1~8
tAS
(See Note 2)
(See Note 5)
tWC
tWP tWR
tCW
tODW
tOEW
Hi-Z
tDS
tDH
VALID DATA IN
(See Note 3)
(See Note 5)
2002-09-18 5/10
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for TC55NEM208AFPN electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ TC55NEM208AFPN.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| TC55NEM208AFPN | The function is TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS. Toshiba Semiconductor | |
| TC55NEM208AFPV | The function is STATIC RAM. Toshiba Semiconductor | |
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