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PDF MC54HC574A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC574A | |
| Descripción | OCTAL 3-STARE NONINVERTING D FLIP-FLOP | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State
Noninverting D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC54/74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the Clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, all device outputs are forced to
the high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HC574A is identical in function to the HCT374A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC574A is the noninverting version of the HC564.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
NON–
INVERTING
OUTPUTS
CLOCK 11
OUTPUT ENABLE 1
PIN 20 = VCC
PIN 10 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDesign Criteria
Value Units
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count*
66.5 ea
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay
1.5 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation
5.0 µW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product
0.0075
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Equivalent to a two–input NAND gate.
pJ
MC54/74HC574A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ Ceramic
MC74HCXXXAN Plastic
MC74HCXXXADW SOIC
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CLOCK
FUNCTION TABLE
Inputs
Output
OE Clock D
Q
L
L
L L,H,
HX
HH
LL
X No Change
XZ
X = Don’t Care
Z = High Impedance
3/97
© Motorola, Inc. 1997
3–1
REV 7
1 page  
tr tf
CLOCK
Q
90%
50%
10%
tw
90%
50%
10%
1/fmax
tPLH tPHL
tTLH tTHL
Figure 1.
SWITCHING WAVEFORMS
MC54/74HC574A
VCC 3.0 V
1.3 V
GND GND
tPZL tPLZ
HIGH
Q
1.3 V
tPZH tPHZ
IMPEDANCE
10% VOL
90% VOH
Q HIGH
IMPEDANCE
Figure 2.
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
EXPANDED LOGIC DIAGRAM
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
CLOCK 11
OUTPUT ENABLE 1
* Includes all probe and jig capacitance
Figure 5. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
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