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PDF ADC081500 Data sheet ( Hoja de datos )
| Número de pieza | ADC081500 | |
| Descripción | A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 2005
ADC081500
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D
Converter
General Description
The ADC081500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits
resolution at sample rates up to 1.7 GSPS. Consuming a
typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this
device is guaranteed to have no missing codes over the full
operating temperature range. The unique folding and inter-
polating architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold ampli-
fier and the self-calibration scheme enable a very flat re-
sponse of all dynamic parameters beyond Nyquist, produc-
ing a high 7.3 ENOB with a 748 MHz input signal and a 1.5
GHz sample rate while providing a 10-18 B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The converter output has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on each bus to
one-half the sample rate.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C ≤ TA ≤ +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 748 MHz Input
n DNL
n Power Consumption
— Operating
— Power Down Mode
8 Bits
1.5 GSPS (min)
10-18 (typ)
7.3 Bits (typ)
±0.15 LSB (typ)
1.2 W (typ)
3.5 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
© 2005 National Semiconductor Corporation DS201531
20153153
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
104 Dd7−
105 Dd7+
106 Dd6−
107 Dd6+
111 Dd5−
112 Dd5+
113 Dd4−
114 Dd4+
115 Dd3−
116 Dd3+
117 Dd2−
118 Dd2+
122 Dd1−
123 Dd1+
124 Dd0
125 Dd0
Equivalent Circuit
Description
The LVDS Data Outputs that are delayed by one CLK cycle in
the output demultiplexer. Compared with the D outputs, these
outputs represent the earlier time sample. These outputs
should always be terminated with a 100Ω differential resistor.
79 OR+
80 OR-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range ±325 mV or ±435 mV as defined by the FSR pin).
82 DCLK+
81 DCLK-
2, 5, 8,
13, 16,
17, 20,
25, 28,
33, 128
40, 51
,62, 73,
88, 99,
110, 121
1, 6, 9,
12, 21,
24, 27,
41
42, 53,
64, 74,
87, 97,
108, 119
VA
VDR
GND
DR GND
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode. The DCLK outputs are not active during a calibration
cycle.
Analog power supply pins. Bypass these pins to ground.
Output Driver power supply pins. Bypass these pins to DR
GND.
Ground return for VA.
Ground return for VDR.
5 www.national.com
5 Page 
Converter Electrical Characteristics (Continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range =
differential 870mVP-P, CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% duty
cycle, VBG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance
= 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6,
7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
tCalDly
Calibration delay determined by See Section 1.1.1, Figure 9,
pin 127
(Note 11)
225 Clock Cycles
(min)
tCalDly
Calibration delay determined by See Section 1.1.1, Figure 9,
pin 127
(Note 11)
231 Clock Cycles
(max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
20153104
Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at TA = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification
Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground
are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: The ADC081500 converter has two LVDS output buses, which each clock data out at one half the sample rate. The second bus (D0 through D7) has a
pipeline latency that is one Input Clock cycle less than the latency of the first bus (Dd0 through Dd7).
Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
11 www.national.com
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