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부품번호 | 54ACT109 기능 |
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기능 | Dual JK Positive Edge-Triggered Flip-Flop | ||
제조업체 | National Semiconductor | ||
로고 | |||
전체 8 페이지수
www.DataSheet4U.com
August 1998
54AC109 • 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n ICC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
DS100267-2
DS100267-7
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100267
www.national.com
DC Characteristics for ’AC Family Devices (Continued)
Symbol
Parameter
ICC Maximum Quiescent
Supply Current
54AC
VCC TA = −55˚C to +125˚C
(V) Guaranteed Limits
5.5 40.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
54ACT
VCC TA = −55˚C to +125˚C
(V) Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
VOL Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
3.70
4.70
0.1
0.1
IIN
ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
Maximum
ICC/Input
(Note 6)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
4.5
5.5
5.5
5.5
5.5
5.5
5.5
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
0.50
0.50
±1.0
1.6
50
−50
40.0
Units
Conditions
µA VIN = VCC
or GND
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
(Note 5)
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA
V IOUT = 50 µA
(Note 5)
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA
µA VI = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
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4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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부품번호 | 상세설명 및 기능 | 제조사 |
54ACT109 | Dual JK Positive Edge-Triggered Flip-Flop | National Semiconductor |
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