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PDF 54AC377 Data sheet ( Hoja de datos )
| Número de pieza | 54AC377 | |
| Descripción | Octal D Flip-Flop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 1999
54AC377 • 54ACT377
Octal D Flip-Flop with Clock Enable
General Description
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n ICC reduced by 50%
n Ideal for addressable register applications
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n Outputs source/sink 24 mA
n See ’273 for master reset version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE® version
n ’ACT377 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC377: 5962-88702
— ’ACT377: 5962-87697
Logic Symbols
IEEE/IEC
DS100290-1
Pin
Names
D0– D7
CE
Q0– Q7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
DS100290-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100290
www.national.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fmax Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn
tPHL Propagation Delay
CP to Qn
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 9)
3.3
5.0
3.3
5.0
3.3
5.0
54AC
TA = −55˚C
to +125˚C
CL = 50 pF
Min Max
75
95
1.0 14.0
1.5 10.0
1.0 15.0
1.5 11.0
AC Operating Requirements
Symbol
Parameter
ts Setup Time, HIGH or LOW
Dn to CP
th Hold Time, HIGH or LOW
Dn to CP
ts Setup Time, HIGH or LOW
CE to CP
th Hold Time, HIGH or LOW
CE to CP
tw CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 3.3 is 3.0V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 10)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
54AC
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed
Minimum
7.5
6.0
1.5
2.5
9.5
6.0
1.0
2.0
6.5
5.0
AC Electrical Characteristics
Symbol
Parameter
fmax Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn
tPHL Propagation Delay
CP to Qn
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 11)
5.0
5.0
5.0
54ACT
TA = −55˚C
to +125˚C
CL = 50 pF
Min Max
85
1.5 11.0
1.5 12.0
Units
MHz
ns
ns
Units
ns
ns
ns
ns
ns
Units
MHz
ns
ns
Fig.
No.
Fig.
No.
Fig.
No.
5 www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 54AC377.PDF ] | |
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