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부품번호 | 54ACT377 기능 |
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기능 | Octal D Flip-Flop | ||
제조업체 | National Semiconductor | ||
로고 | |||
전체 8 페이지수
www.DataSheet4U.com
February 1999
54AC377 • 54ACT377
Octal D Flip-Flop with Clock Enable
General Description
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n ICC reduced by 50%
n Ideal for addressable register applications
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n Outputs source/sink 24 mA
n See ’273 for master reset version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE® version
n ’ACT377 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC377: 5962-88702
— ’ACT377: 5962-87697
Logic Symbols
IEEE/IEC
DS100290-1
Pin
Names
D0– D7
CE
Q0– Q7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
DS100290-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100290
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DC Characteristics for ’AC Family Devices (Continued)
Symbol
Parameter
IOLD
IOHD
ICC
(Note 4)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
54AC
VCC
TA =
(V) −55˚C to +125˚C
Guaranteed Limits
5.5 50
5.5 −50
5.5 80.0
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
54ACT
VCC
TA =
(V) −55˚C to +125˚C
Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
VOL Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
3.70
4.70
0.1
0.1
IIN
ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
Maximum
ICC/Input
(Note 7)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
4.5
5.5
5.5
5.5
5.5
5.5
5.5
Note 6: *All outputs loaded; thresholds on input associated with output under test.
Note 7: †Maximum test duration 2.0 ms, one output loaded at a time.
Note 8: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
0.50
0.50
±1.0
1.6
50
−50
80.0
Units
mA
mA
µA
Units
V
V
V
V
V
V
µA
mA
mA
mA
µA
Conditions
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
or GND
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
(Note 6)
VIN = VIL or VIH
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
(Note 6)
VIN = VIL or VIH
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
or GND
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4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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구 성 | 총 8 페이지수 | ||
다운로드 | [ 54ACT377.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
54ACT373 | Octal Transparent Latch | National Semiconductor |
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |