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부품번호 54ACQ373 기능
기능 Quiet Series Octal Transparent Latch
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54ACQ373 데이터시트, 핀배열, 회로
www.DataSheet4U.com
September 1998
54ACQ373 54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE®
Outputs
General Description
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT373
n 4 kV minimum ESD immunity (’ACQ)
n Standard Military Drawing (SMD)
— ’ACTQ373: 5962-92188
— ’ACQ373: 5962-92178
Logic Symbols
IEEE/IEC
DS100238-1
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
DS100238-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100238
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54ACQ373 pdf, 반도체, 판매, 대치품
DC Characteristics for ’ACQ Family Devices (Continued)
54ACQ
Symbol
Parameter
VCC
TA =
(V) −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
IOLD
Minimum Dynamic
(Note 3)
5.5
50
mA VOLD = 1.65V Max
IOHD
ICC
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
−50
80.0
mA VOHD = 3.85V Min
µA VIN = VCC
or GND (Note 4)
IOZ
VOLP
VOLV
Maximum TRI-STATE
Leakage Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Maximum Dynamic VOL
5.5
5.0
5.0
±5.0
1.5
−1.2
VI(OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
V
(Notes 5, 6)
V
(Notes 5, 6)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54ACQ @ 25˚C is identical to 74ACQ @ 25˚C.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
54ACTQ
VCC
TA =
(V) −55˚C to +125˚C
Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
VOL Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
3.70
4.70
0.1
0.1
4.5
5.5
IIN Maximum Input
Leakage Current
5.5
IOZ Maximum TRI-STATE 5.5
Leakage Current
0.50
0.50
±1.0
±5.0
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
(Note 8)
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA
V IOUT = 50 µA
(Note 8)
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
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54ACQ373 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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