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54ACTQ374 데이터시트 PDF




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부품번호 54ACTQ374 기능
기능 Quiet Series Octal D Flip-Flop
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54ACTQ374 데이터시트, 핀배열, 회로
www.DataSheet4U.com
August 1998
54ACQ374 54ACTQ374
Quiet Series Octal D Flip-Flop with TRI-STATE® Outputs
General Description
The ’ACQ/’ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and TRI-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICC and IOZ reduced by 50%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered positive edge-triggered clock
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT374
n 4 kV minimum ESD immunity
n Standard Military Drawing (SMD)
— ’ACTQ374: 5962-92189
— ’ACQ374: 5962-92179
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
and Flatpak
IEEE/IEC
DS100239-1
DS100239-3
Pin Assignment for LCC
DS100239-2
GTOis a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Seriesis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100239
DS100239-4
www.national.com




54ACTQ374 pdf, 반도체, 판매, 대치품
DC Characteristics for ’ACQ Family Devices (Continued)
54ACQ
Symbol
Parameter
VCC
TA = −55˚C to +125˚C
Units
(V) Guaranteed Limits
Conditions
ICC Maximum Quiescent
Supply Current
5.5
80.0
µA VIN = VCC
or GND (Note 5)
IOZ
VOLP
VOLV
Maximum TRI-STATE
Leakage Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
5.5
5.0
5.0
±5.0
1.5
−1.2
VI(OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
V
(Notes 6, 7)
V
(Notes 6, 7)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54ACQ @ 25˚C is identical to 74ACQ @ 25˚C.
Note 6: Plastic DIP Package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 8: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
54ACTQ
VCC TA = −55˚C to +125˚C
(V) Guaranteed Limits
4.5 2.0
5.5 2.0
4.5 0.8
5.5 0.8
4.5 4.4
5.5 5.4
VOL Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
3.70
4.70
0.1
0.1
IIN
IOZ
ICCT
IOLD
IOHD
Maximum Input
Leakage Current
Maximum TRI-STATE
Current
Maximum ICC/Input
(Note 9)
Minimum Dynamic
Output Current
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.50
0.50
±1.0
±5.0
1.6
50
−50
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
(Note 9)
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA
V IOUT = 50 µA
(Note 9)
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
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54ACTQ374 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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