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PDF MAX5550 Data sheet ( Hoja de datos )
| Número de pieza | MAX5550 | |
| Descripción | High-Output-Current DAC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3871; Rev 0; 10/05
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
General Description
The MAX5550 dual, 10-bit, digital-to-analog converter
(DAC) features high-output-current capability. The
MAX5550 sources up to 30mA per DAC, making it ideal
for PIN diode biasing applications. Outputs can also be
paralleled for high-current applications (up to 60mA
typ). Operating from a single +2.7V to +5.25V supply,
the MAX5550 typically consumes 1.5mA per DAC in
normal operation and less than 1µA (max) in shutdown
mode. The MAX5550 also features low output leakage
current in shutdown mode (±1µA max) that is essential
to ensure that the external PIN diodes are off.
Additional features include an integrated +1.25V
bandgap reference, and a control amplifier to ensure
high accuracy and low-noise performance. A separate
reference input (REFIN) allows for the use of an external
reference source, such as the MAX6126, for improved
gain accuracy. A pin-selectable I2C*-/SPI™-compatible
serial interface provides optimum flexibility for the
MAX5550. The maximum programmable output current
value is set using software and an adjustment resistor.
The MAX5550 is available in a (3mm x 3mm) 16-pin thin
QFN package, and is specified over the extended
(-40°C to +85°C) temperature range.
Applications
PIN Diode Biasing
RF Attenuator Control
VCO Tuning
Features
♦ Pin-Selectable I2C- or SPI-Compatible Interface
♦ Guaranteed Low Output Leakage Current in
Shutdown (±1µA max)
♦ Guaranteed Monotonic over Extended
Temperature Range
♦ Dual Outputs for Balanced Systems
♦ Current Outputs Source Up to 30mA per DAC
♦ Parallelable Outputs for 60mA Applications
♦ Output Stable with RF Filters
♦ Internal or External Reference Capability
♦ Digital Output (DOUT) Available for Daisy
Chaining in SPI Mode
♦ +2.7V to +5.25V Single-Supply Operation
♦ 16-Pin (3mm x 3mm) Thin QFN Package
♦ Programmable Output Current Range Set by
Software and Adjustment Resistor
Ordering Information
PART
TEMP PIN-
RANGE PACKAGE
PKG
CODE
TOP
MARK
MAX5550ETE
-40°C to
+85°C
16 Thin QFN T1633F-3
ACZ
Functional Diagram
REFIN
VDD
+1.25V
REF
BUFFER
10-BIT CURRENT-STEERING
DAC A
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
SPI is a trademark of Motorola, Inc.
Pin Configuration appears at end of data sheet.
MAX5550
DAC REGISTER A
DAC REGISTER B
10-BIT CURRENT-STEERING
DAC B
SPI/I2C
16-BIT INPUT REGISTER
SCLK/SCL DIN/SDA CS/A0 DOUT/A1
GND
P
OUTA
FSADJA
VDD
P
OUTB
FSADJB
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
Typical Operating Characteristics
(VDD = +3.0V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20kΩ, TA = +25°C. unless otherwise noted).
INL vs. CODE
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
128 256 384 512 640 768 896 1024
CODE
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
-40
DNL vs. TEMPERATURE
-15 10 35 60
TEMPERATURE (°C)
85
DNL vs. CODE
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
128 256 384 512 640 768 896 1024
CODE
MAXIMUM INL ERROR vs.
OUTPUT CURRENT RANGES
3.0
2.5
2.0
1.5
1.0
0.5
0
1–2 1.5–3 2–5 4.5–9 8–16 15–30
OUTPUT CURRENT RANGE (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40
INL vs. TEMPERATURE
-15 10 35 60
TEMPERATURE (°C)
85
ZERO-SCALE OUTPUT CURRENT
vs. TEMPERATURE
4.5
4.0
3.5
3.0
VDD = 5V
2.5
2.0
1.5
1.0 VDD = 3V
0.5
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
FULL-SCALE CURRENT vs. TEMPERATURE
29.88
29.86
29.84
VDD = 5V
29.82
29.80
29.78
29.76
VDD = 3V
29.74
29.72
-40
-15 10 35 60
TEMPERATURE (°C)
85
SETTLING TIME
(FULL-SCALE POSITIVE STEP)
MAX5550 toc08
CS
2V/div
RLOAD = 65Ω
CLOAD = 24pF
10µs/div
VOUT_
1V/div
SETTLING TIME
(FULL-SCALE NEGATIVE STEP)
MAX5550 toc09
CS
2V/div
RLOAD = 65Ω
CLOAD = 24pF
VOUT_
1V/div
10µs/div
_______________________________________________________________________________________ 5
5 Page 
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
S
SDA
SCL 1 2
ACKNOWLEDGE
8
9
Figure 5. Acknowledge Condition
Table 3. Write Operation
S
T
A ADDRESS
R BYTE
T R/ W*
COMMAND/DATA BYTE
DATA BYTE
S
T
O
P
Master
SDA
S
0
1
1
0
0 A1 A0 0
C5 C4 C3 C2 C1 C0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0 P
Slave
SDA
A
C
K
AA
CC
KK
*Read operation not supported.
Slave Address
A master initiates communication with a slave device
by issuing a START condition followed by a slave
address (see Table 3). The slave address consists of 7
address bits and a read/write bit (R/W). When idle, the
device continuously waits for a START condition fol-
lowed by its slave address. When the device recog-
nizes its slave address, it acquires the data and
executes the command. The first 5 bits (MSBs) of the
slave address have been factory programmed and are
always 01100. Connect A1 and A0 to VDD or GND to
program the remaining 2 bits of the slave address. Set
the least significant bit (LSB) of the address byte (R/W)
to zero to write to the MAX5550. After receiving the
address, the MAX5550 (slave) issues an acknowledge
by pulling SDA low for one clock cycle. I2C read com-
mands (R/W = 1) are not acknowledged by the
MAX5550.
Write Cycle
The write command requires 27 clock cycles. In write
mode (R/W = 0), the command/data byte that follows
the address byte controls the MAX5550 (Table 3). The
registers update on the rising edge of the 26th SCL
pulse. Prematurely aborting the write cycle does not
update the DAC. See Table 4 for a command summary.
SPI Compatibility (SPI/I2C = VDD)
The MAX5550 is compatible with the 3-wire SPI serial
interface (Figure 6). This interface mode requires three
inputs: chip-select (CS), data clock (SCLK), and data in
(DIN). Drive CS low to enable the serial interface and
clock data synchronously into the shift register on each
SCLK rising edge.
The MAX5550 requires 16 clock cycles to clock in 6
command bits (C5–C0) and 10 data bits (D9–D0)
(Figure 7). After loading data into the shift register,
drive CS high to latch the data into the appropriate
DAC register and disable the serial interface. Keep CS
low during the entire serial data stream to avoid corrup-
tion of the data. See Table 4 for a command summary.
Shutdown Mode
The MAX5550 has a software shutdown mode that
reduces the supply current to less than 1µA. Shutdown
mode disables the DAC outputs. The serial interface
remains active in shutdown. This provides the flexibilty to
update the registers while in shut down. Recycling the
power supply resets the device to the default settings.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAX5550.PDF ] | |
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