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PDF XRT86VL3X Data sheet ( Hoja de datos )
| Número de pieza | XRT86VL3X | |
| Descripción | T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION | |
| Fabricantes | Exar Corporation | |
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XRT86VL3x
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
JULY 2006
REV. 1.2.0
GENERAL DESCRIPTION
The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s
DS1/E1/J1 framer and LIU integrated solution
featuring R3 technology (Relayless, Reconfigurable,
Redundancy) that comes in a 2-channel, 4-channel,
or 8-channel package. The physical interface is
optimized with internal impedance, and with the
patented pad structure, the XRT86VL3x provides
protection from power failures and hot swapping.
The XRT86VL3x contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VL3x fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT86VL3X N-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
XRT86VL3x
1 of N-channels
Tx Serial
Clock
Tx Serial
Data In
Rx Serial
Clock
Rx Serial
Data Out
PRBS
Generator &
Analyser
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC/LAPD
Controllers
Tx LIU
Interface
LLB LB
Rx LIU
Interface
LIU &
Loopback
Control
TTIP
TRING
RTIP
RRING
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Signaling &
Alarms
System (Terminal) Side
TxON
JTAG
DMA
Interface
Microprocessor
Interface
INT
Memory
D[7:0]
3
A[14:0]
µP
Select
4 WR
ALE_AS
RD
RDY_DTACK
Intel/Motorola µP
Configuration, Control &
Status Monitor
1:2 Turns Ratio
1:1 Turns Ratio
RxLOS
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT86VL3X
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE .......................................................................... 31
3.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-
NALING (R) BITS IN T1DM FRAMING FORMAT MODE ............................................................................................. 32
3.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ........................................................................... 33
3.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 33
3.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY
DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ...................................................................................... 33
3.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE .......................................................................... 35
3.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE
SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ....................................................................................... 36
3.3 E1 OVERHEAD INTERFACE BLOCK .............................................................................................................. 37
3.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................... 37
3.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................... 37
3.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-
QUENCE IN E1 FRAMING FORMAT MODE ................................................................................................................ 38
3.5 E1 RECEIVE OVERHEAD INTERFACE ........................................................................................................... 41
3.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ................................................. 41
3.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT
SEQUENCE IN E1 FRAMING FORMAT MODE ............................................................................................................ 41
4.0 LIU TRANSMIT PATH ........................................................................................................................... 43
4.1 TRANSMIT DIAGNOSTIC FEATURES ............................................................................................................. 43
4.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................... 43
4.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ........................................................................................................... 43
4.1.3 NETWORK LOOP UP CODE ........................................................................................................................................ 43
4.1.4 NETWORK LOOP DOWN CODE ................................................................................................................................. 44
4.1.5 QRSS GENERATION .................................................................................................................................................... 44
4.2 T1 LONG HAUL LINE BUILD OUT (LBO) ........................................................................................................ 44
4.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ...................................................................................................... 47
4.3.1 ARBITRARY PULSE GENERATOR ............................................................................................................................. 47
4.3.2 DMO (DIGITAL MONITOR OUTPUT) ........................................................................................................................... 48
4.3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................................. 48
4.4 LINE TERMINATION (TTIP/TRING) .................................................................................................................. 48
5.0 LIU RECEIVE PATH .............................................................................................................................. 49
5.1 LINE TERMINATION (RTIP/RRING) ................................................................................................................. 49
5.1.1 INTERNAL TERMINATION ........................................................................................................................................... 49
5.1.2 EQUALIZER CONTROL ............................................................................................................................................... 49
5.1.3 CABLE LOSS INDICATOR ........................................................................................................................................... 50
5.2 RECEIVE SENSITIVITY ..................................................................................................................................... 50
5.2.1 AIS (ALARM INDICATION SIGNAL) ............................................................................................................................ 51
5.2.2 NLCD (NETWORK LOOP CODE DETECTION) ........................................................................................................... 51
5.2.3 FLSD (FIFO LIMIT STATUS DETECTION) .................................................................................................................. 52
5.2.4 RECEIVE JITTER ATTENUATOR ................................................................................................................................ 52
5.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ..................................................................................................... 52
6.0 THE E1 TRANSMIT/RECEIVE FRAMER .............................................................................................. 54
6.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK .................... 54
6.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
XRT84V24 COMPATIBLE 2.048MBIT/S MODE ........................................................................................................... 54
6.2 TRANSMIT/RECEIVE HIGH-SPEED BACK-PLANE INTERFACE .................................................................. 56
6.2.1 NON-MULTIPLEXED HIGH-SPEED MODE ................................................................................................................. 56
6.2.2 MULTIPLEXED HIGH-SPEED MODE .......................................................................................................................... 59
6.3 BRIEF DISCUSSION OF COMMON CHANNEL SIGNALING IN E1 FRAMING FORMAT .............................. 65
6.4 BRIEF DISCUSSION OF CHANNEL ASSOCIATED SIGNALING IN E1 FRAMING FORMAT ....................... 65
6.5 INSERT/EXTRACT SIGNALING BITS FROM TSCR REGISTER .................................................................... 65
6.6 INSERT/EXTRACT SIGNALING BITS FROM TXCHN[0]_N/TXSIG PIN ......................................................... 65
6.7 ENABLE CHANNEL ASSOCIATED SIGNALING AND SIGNALING DATA SOURCE CONTROL ................. 66
7.0 THE DS1 TRANSMIT/RECEIVE FRAMER ............................................................................................ 67
7.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK .................... 67
7.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
1.544MBIT/S MODE ....................................................................................................................................................... 67
7.2 TRANSMIT/RECEIVE HIGH-SPEED BACK-PLANE INTERFACE .................................................................. 69
7.2.1 T1 TRANSMIT/RECEIVE INTERFACE - MVIP 2.048 MHZ .......................................................................................... 69
7.2.2 NON-MULTIPLEXED HIGH-SPEED MODE ................................................................................................................. 70
7.2.3 MULTIPLEXED HIGH-SPEED MODE .......................................................................................................................... 72
II
5 Page 
XRT86VL3X
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
1.0 GENERAL DESCRIPTION AND INTERFACE
The XRT86VL3x supports multiple interfaces for various modes of operation. The purpose of this section is to
present a general overview of the common interfaces and their connection diagrams. Each mode will be
described in full detail in later sections of the datasheet.
NOTE: For a brief tutorial on Framing Formats, see Appendix A in the back of this document.
1.1 Physical Interface
The Line Interface Unit generates/receives standard return-to-zero (RZ) signals to the line interface for T1/E1/
J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating impedance
inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external
components necessary in system design. The transmitter outputs only require one DC blocking capacitor of
0.68µF and a 1:2 step-up transformer. The receive path inputs only require one bypass capacitor of 0.1µF
connected to the center tap (CT) of the transformer and a 1:1 transformer. The receive CT bypass capacitor is
required for Long Haul Applications, and recommended for Short Haul Applications. Figure 2 shows the
typical connection diagram for the LIU transmitters. Figure 3 shows a typical connection diagram for the LIU
receivers.
FIGURE 2. LIU TRANSMIT CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT86VL3x LIU
TTIP
Transmitter
Output
TRING
Internal Impedance
C=0.68uF
1:2
Line Interface T1/E1/J1
One Bill of Materials
FIGURE 3. LIU RECEIVE CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT86VL3x LIU
RTIP
Receiver
Input
R RING
Internal Impedance
0.1µF
1:1
Line Interface T1/E1/J1
One Bill of Materials
4
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT86VL3X.PDF ] | |
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