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부품번호 | LXP730 기능 |
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기능 | Multi-Rate DSL Framer | ||
제조업체 | Intel Corporation | ||
로고 | |||
전체 30 페이지수
www.DataSheet4U.com
LXP730
Multi-Rate DSL Framer
Datasheet
The LXP730 is a multi-purpose Digital Subscriber Line (DSL) framer which complements the
Level One SK70725/21 Enhanced MDSL Data Pump (EMDP) to provide seamless transport of
data and voice signals over one or more DSL datapaths.
Applications
The LXP730 in combination with the EMDP
chipset is optimized for use as a framer or I/O
interface device for the following applications:
s Digital Pair Gain Systems
s Ethernet Modems
s T1/E1 Fractional Transport Systems
s Videoconferencing Systems
s Simultaneous Data - Voice Transport
Systems
s Wireless Base Station Access Systems
Product Features
The LXP730 provides the basic functions
required of a DSL framer:
s Synchronization of external data streams to
the DSL line
s Multiplexing and demultiplexing of
independent data streams for voice and data
s Loopback of payload data at the DSL
interface
s Creation, insertion, and recovery of the
MDSL Overhead (MOH) structure,
performance monitoring, and message
transport required in a DSL system with a
capacity of up to 32 kbps
s Supports two input/output data streams
simultaneously
— Slave mode: external clock determines
the rate at which data will be transferred
to and from the framer
— Master mode: clock derived from
received DSL clock or external
oscillator
s Single part architecture allows one chip to
be used economically in both central and
remote locations
s Supports systems with point-to-point
architectures
s Alternate Hardware Control mode (HWC)
for operation without an external
microprocessor
As of January 15, 2001, this document replaces the Level One document
LXP730 Multi-Rate DSL Framer Datasheet.
Order Number: 249266-001
January 2001
LXP730 — Multi-Rate DSL Framer
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.2.9 Channel 9............................................................................................... 51
5.2.10 Channel 10............................................................................................. 52
5.2.11 Channel 11............................................................................................. 52
5.2.12 Channel 12............................................................................................. 52
5.2.13 Channel 13............................................................................................. 53
5.2.14 Channel 14............................................................................................. 53
5.2.15 Channel 15............................................................................................. 53
5.2.16 Channel 16............................................................................................. 54
5.2.17 Channel 17............................................................................................. 54
5.2.18 Channel 18............................................................................................. 54
Reserved Registers (3 bytes).............................................................................. 55
Wander Reduction Register ................................................................................ 55
FIFO/Miscellaneous Control Register ................................................................. 55
Slip Buffer Lower Threshold Register ................................................................. 56
Slip Buffer Upper Threshold Register ................................................................. 57
Version Register.................................................................................................. 57
Internal Clock Control Registers (4 bytes) .......................................................... 57
5.9.1 ADPLL Control 1 .................................................................................... 57
5.9.2 ADPLL Control 2 .................................................................................... 58
5.9.3 ADPLL Control 3 .................................................................................... 58
5.9.4 MCLK Divide .......................................................................................... 58
Programmable Idle Code Byte ............................................................................ 58
PCM Configuration Registers.............................................................................. 59
5.11.1 PCM1 Configuration ............................................................................... 59
5.11.2 PCM2 Configuration ............................................................................... 59
Codec Configuration Register ............................................................................. 60
Overhead Registers (25 bytes) ........................................................................... 60
5.13.1 Miscellaneous Control ............................................................................ 60
5.13.2 Overhead Configuration ......................................................................... 61
5.13.3 CRC Error Counter................................................................................. 61
5.13.4 FEBE Error Counter ............................................................................... 62
5.13.5 CRC - FEBE - LOS Status ..................................................................... 62
5.13.6 MX Overhead Bits 1 - 8.......................................................................... 62
5.13.7 MX Overhead Bits 9 - 16 ........................................................................ 63
5.13.8 MX Overhead Bits 17 - 24 ...................................................................... 63
5.13.9 MX Overhead Bits 25 - 32 ...................................................................... 63
5.13.10 MX Z Bits 1 - 8 ....................................................................................... 64
5.13.11 MX Z Bits 9 - 16 ..................................................................................... 64
5.13.12 MX Z Bits 17 - 24 ................................................................................... 64
5.13.13 MX Z Bits 25 - 32 ................................................................................... 65
5.13.14 MX Z Bits 33 - 40 ................................................................................... 65
5.13.15 MX Z Bits 41 - 48 ................................................................................... 65
5.13.16 DX Overhead Bits 1 - 8 .......................................................................... 65
5.13.17 DX Overhead Bits 9 - 16 ........................................................................ 66
5.13.18 DX Overhead Bits 17 - 24 ...................................................................... 66
5.13.19 DX Overhead Bits 25 - 32 ...................................................................... 66
5.13.20 DX Z Bits 1 - 8........................................................................................ 67
5.13.21 DX Z Bits 9 - 16 ...................................................................................... 67
5.13.22 DX Z Bits 17 - 24 .................................................................................... 67
5.13.23 DX Z Bits 25 - 32 .................................................................................... 68
4 Datasheet
4페이지 Multi-Rate DSL Framer — LXP730
50 Version ................................................................................................................57
51 ADPLL Control 1 .................................................................................................57
52 ADPLL Control 2 .................................................................................................58
53 PROG Divide.......................................................................................................58
54 Programmable Idle Code Byte ............................................................................59
55 PCM 1 Configuration Bits ....................................................................................59
56 PCM 2 Configuration Bits ....................................................................................60
57 Codec Configuration............................................................................................60
58 Miscellaneous Control .........................................................................................60
59 Overhead Configuration ......................................................................................61
60 CRC Error Counter..............................................................................................62
61 FEBE Error Counter ............................................................................................62
62 CRC - FEBE Status.............................................................................................62
63 MX Overhead Bits 1 - 8 .......................................................................................63
64 MX Overhead Bits 9 - 16 .....................................................................................63
65 MX Overhead Bits 17 - 24 ...................................................................................63
66 MX Overhead Bits 25 - 32 ...................................................................................64
67 MX Z Bits 1 - 8.....................................................................................................64
68 MX Z Bits 9 - 16...................................................................................................64
69 MX Z Bits 17 - 24.................................................................................................64
70 MX Z Bits 25 - 32.................................................................................................65
71 MX Z Bits 33 - 40.................................................................................................65
72 MX Z Bits 41 - 48.................................................................................................65
73 DX Overhead Bits 1 - 8 .......................................................................................66
74 DX Overhead Bits 9 - 16 .....................................................................................66
75 DX Overhead Bits 17 - 24 ...................................................................................66
76 DX Overhead Bits 25 - 32 ...................................................................................67
77 DX Z Bits 1 - 8 .....................................................................................................67
78 DX Z Bits 9 - 16 ...................................................................................................67
79 DX Z Bits 17 - 24 .................................................................................................67
80 DX Z Bits 25 - 32 .................................................................................................68
81 DX Z Bits 33 - 40 .................................................................................................68
82 DX Z Bits 41 - 48 .................................................................................................68
83 Reserved Registers.............................................................................................68
84 Interrupt Enables .................................................................................................69
85 Interrupt Status....................................................................................................69
Datasheet
7
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LXP730 | Multi-Rate DSL Framer | Intel Corporation |
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