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PDF A3984 Data sheet ( Hoja de datos )

Número de pieza A3984
Descripción DMOS Microstepping Driver
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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A3984
DMOS Microstepping Driver with Translator
Package LP
The A3984 is a complete microstepping motor driver with built-in
translator for easy operation. It is designed to operate bipolar stepper
motors in full-, half-, quarter-, and sixteenth-step modes, with an output
drive capacity of up to 35 V and ±2 A. The A3984 includes a fixed off-
time current regulator which has the ability to operate in Slow or Mixed
decay modes.
CP1 1
CP2 2
VCP 3
VREG 4
MS1 5
MS2 6
RESET 7
ROSC 8
SLEEP 9
VDD 10
STEP 11
REF 12
24 GND
23 ENABLE
22 OUT2B
21 VBB2
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 DIR
13 GND
The translator is the key to the easy implementation of the A3984.
Simply inputting one pulse on the STEP input drives the motor one
microstep. There are no phase sequence tables, high frequency control
lines, or complex interfaces to program. The A3984 interface is an ideal
fit for applications where a complex microprocessor is unavailable or is
overburdened.
The chopping control in the A3984 automatically selects the current
decay mode (Slow or Mixed). When a signal occurs at the STEP input
pin, the A3984 determines if that step results in a higher or lower
current in each of the motor phases. If the change is to a higher current,
then the decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially to a fast
decay for a period amounting to 31.25% of the fixed off-time, then
to a slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Approximate Scale 1:1
Internal circuit protection includes: thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current protection.
Special power-on sequencing is not required.
ABSOLUTE MAXIMUM RATINGS
The A3984 is supplied in a low-profile (1.2 mm maximum), 24-pin
TSSOP with exposed thermal pad (package LP). It is also available
Load Supply Voltage,VBB ...................................35 V
Output Current, IOUT......................................... ±2 A*
Logic Input Voltage, VIN ..................... –0.3 V to 7 V
Sense Voltage, VSENSE .......................................0.5 V
Reference Voltage, VREF ……….. ........................4 V
Operating Temperature Range
Ambient, TA ................................. –20°C to 85°C
in a lead (Pb) free version (suffix –T), with 100% matte tin plated
leadframes.
FEATURES
Low RDS(ON) outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Junction Temperature, TJ(MAX)..................... 150°C
Crossover-current protection
Storage Temperature, TS .................... –55°C to 150°C Selection Guide
*Output current rating may be limited by duty cycle,
Part Number Pb-free*
Package
Packing
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified current
rating or a junction temperature of 150°C.
A3984SLP-T
Yes 24-pin TSSOP
62 per tube
A3984SLPTR-T
Yes 24-pin TSSOP
4000 per reel
*Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be LAST TIME BUY.
This classification indicates that sale of this device is currently restricted to existing
customer applications. The variants should not be purchased for new design applications
because obsolescence in the near future is probable. Samples are no longer available.
Status change: October 31, 2006. Deadline for receipt of LAST TIME BUY orders:
April 27, 2007. These variants include: A3984SLP and A3984SLPTR.
26184.30Bpb

1 page




A3984 pdf
A3984
DMOS Microstepping Driver with Translator
STEP
MS1, MS2,
RESET, or DIR
tA
tC tD
tB
Time Duration
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
Figure 1. Logic Interface Timing Diagram
Symbol
tA
tB
tC
tD
Typ.
1
1
200
200
Unit
μs
μs
ns
ns
Table 1. Microstep Resolution Truth Table
MS1 MS2 Microstep Resolution Excitation Mode
L L Full Step
2 Phase
H L Half Step
1-2 Phase
L H Quarter Step
W1-2 Phase
H H Sixteenth Step
4W1-2 Phase
26184.30A
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

5 Page





A3984 arduino
A3984
DMOS Microstepping Driver with Translator
Pin List Table
Name
Description
Number
CP1 Charge pump capacitor 1
1
CP2 Charge pump capacitor 2
2
VCP
Reservoir capacitor
3
VREG
Regulator decoupling
4
MS1
Logic input
5
MS2
Logic input
6
RESET Logic input
7
ROSC
Timing set
8
SLEEP Logic input
9
VDD
Logic supply
10
STEP
Logic input
11
REF
Current trip reference voltage input
12
GND
Ground*
13
DIR Logic input
14
OUT1B DMOS Full Bridge 1 Output B
15
VBB1
Load supply
16
SENSE1 Sense resistor for Bridge 1
17
OUT1A DMOS Full Bridge 1 Output A
18
OUT2A DMOS Full Bridge 2 Output A
19
SENSE2 Sense resistor for Bridge 2
20
VBB2
Load supply
21
OUT2B DMOS Full Bridge 2 Output B
22
ENABLE Logic input
23
GND
Ground*
24
*The two GND pins must be tied together externally by connecting
to the exposed pad ground plane under the device.
26184.30A
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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