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PDF AL103 Data sheet ( Hoja de datos )
| Número de pieza | AL103 | |
| Descripción | 8 PORT LOW COST 10/100 SWITCH | |
| Fabricantes | Allayer | |
| Logotipo |  |
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AL103
Revision 1.0
8 PORT LOW COST 10/100 SWITCH
• Supports 8 10/100 Mbit/s MII ports
• Port monitoring support
• Capable of trunking up to 800 Mbit/s link • IEEE 802.3x flow control for full-duplex
• Trunk fail-over feature
operation
• Full- and half-duplex mode operation
• Optional backpressure flow control sup-
• Speed auto-negotiation through MDIO
port for half-duplex operation
• Built-in storage of 1K MAC addresses
• Design to utilize low-cost SGRAM
• Serial EEPROM interface for low-cost
system configuration
• Supports store-and-forward mode
switching
• VLAN support
• AL102A pin compatible
• Automatic source address learning
• 3.3V operation
• Secure mode traffic filtering
• Packaged in 256-pin PQFP
• Broadcast storm control
Product Description
The AL103 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet
switch can be implemented using the AL103 with low-cost SGRAM. The AL103 also supports
VLAN and multiple port aggregation trunks.
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
High Speed
Switch Fabric
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
Figure 1 System Block Diagram
Switch
Controller
Address
Control
Address
Table
Buffer
Manager
EEPROM
Interface
Reference Only / Allayer Communications
1 page  
AL103 Revision 1.0
1. AL103 Overview
The AL103 provides eight 10/100 Mbit/s Ethernet ports. Each port supports both 10 and 100
Mbit/s data rate. The operation mode is auto-negotiated by the PHY. All ports are full-duplex
capable. The device also supports VLAN for workgroup and segment switching applications.
The AL103 also supports trunking applications. The chip provides two optional load-balancing
schemes, explicit and dynamic. With trunking, it is possible to group up to four full-duplex links
together to form a single 800 Mbit/s link.
Data received from the MAC interface is stored in the external memory buffer. The AL103 utilizes
cost effective SGRAM to provide 8-Mbit or 16-Mbit of buffer memory.
During transmission, the data is obtained from the buffer memory and routed to the destination
port’s output buffer. If a collision occurs in half-duplex operation, the MAC control will back off
and retransmit in accordance to the IEEE 802.3 specification.
The AL103 provides two flow control methods. For half-duplex operations, an optional jamming
based flow control (known as backpressure) is available to prevent loss of data. With this method of
flow control, the switch will generate a jam signal when the receive buffer is full and the sending
station will not start to transmit until the line is clear. In the full-duplex mode, the AL103 utilizes
IEEE 802.3x as the flow control mechanism.
All ports support multiple MAC addresses. The switch chip supports 1K MAC addresses internally.
These MAC addresses are shared among all eight ports.
The initialization and configuration of the switch is programmed by an external EEPROM. Field
reconfiguration can be achieved by using a parallel interface to reprogram the EEPROM.
The AL103 also supports port based VLAN. The VLAN register set is used to configure the
destination ports for multicast and broadcast frames.
The device also provides two levels of security for intrusion protection. Security can be
implemented on a per port basis.
The AL103 operates only in the store and forward mode. The entire frame is checked for error and
any frames with errors are automatically filtered and will not be forwarded to the destination port.
The AL103 also features port monitoring and broadcast storm throttling.
9/00
Reference Only / Allayer Communications
5
5 Page 
AL103 Revision 1.0
M6TXCLK
M6RXD3
M6RXD2
M6RXD1
M6RXD0
M6RXDV
M6RXCLK
M6RXER
M6CRS
M6COL
Table 7: MII Interface Port 6 (Continued)
158 I Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
166 I Receive Data - NRZ data from the transceiver.
164 For MII interface, signal RX_DV, RX_ER and RX_D0 through
163 RX_D3 are sampled by the rising edge of RX_CLK.
162
161 I Receive Data Valid.
160 I Receive Clock.
159 I Receive Data Error.
148 I Carrier Sense.
150 I Collision Detect.
PIN
NAME
M7TXD3
M7TXD2
M7TXD1
M7TXD0
M7TXEN
M7TXCLK
M7RXD3
M7RXD2
M7RXD1
M7RXD0
M7RXDV
M7RXCLK
M7RXER
M7CRS
M7COL
PIN
NUMBER
174
175
176
178
179
180
188
186
185
184
183
182
181
170
172
Table 8: MII Interface Port 7
I/O DESCRIPTION
O Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
O Transmit Enable.
Synchronous to the transmit clock.
I Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
I Receive Data - NRZ data from the transceiver.
For MII interface, signal RX_DV, RX_ER and RX_D0 through
RX_D3 are sampled by the rising edge of RX_CLK.
I Receive Data Valid.
I Receive Clock.
I Receive Data Error.
I Carrier Sense.
I Collision Detect.
9/00
Reference Only / Allayer Communications
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AL103.PDF ] | |
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