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M5M5V416CWG-55HI 데이터시트 PDF




Renesas Technology에서 제조한 전자 부품 M5M5V416CWG-55HI은 전자 산업 및 응용 분야에서
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부품번호 M5M5V416CWG-55HI 기능
기능 CMOS STATIC RAM
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M5M5V416CWG-55HI 데이터시트, 핀배열, 회로
2003.08.21 Ver. 7.0
www.DataSheet4U.com
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs - Single 2.7~3.6V power supply
organized as 262144-words by 16-bit, f abricated by Renesas's - Small stand-by current: 0.2µA (3.00V, ty p.)
high-perf ormance 0.18µm CMOS technology .
- No clocks, No ref resh
The M5M5V416C is suitable f or memory applications where a
- Data retention supply v oltage =2.0V
simple interf acing , battery operating and battery backup are the - All inputs and outputs are TTL compatible.
important design objectiv es.
- Easy memory expansion by S1#, S2, BC1# and BC2#
M5M5V416CWG is packaged in a CSP (chip scale package),
- Common Data I/O
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) - Three-state outputs: OR-tie capability
and ball pitch of 0.75mm. It giv es the best solution f or
- OE# prev ents data contention in the I/O bus
a compaction of m ounting area as well as f lexibility of wiring
- Process technology : 0.18µm CMOS
pattern of printed circuit boards.
- Package: 48ball 7.0mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-version
-40 ~ +85°C
M5M5V416CWG -55HI
M5M5V416CWG -70HI
Power
Supply
Access time
max.
Stand-by c urrent (µA)
* Typical(3.0V)
Ratings (max. @3.6V)
25°C 40°C Voltage 25°C 40°C 70°C 85°C
Activ e
current
Icc1
(3.0V, ty p.)
2.7 ~ 3.6V
55ns
70ns
3.0V 1.0 2.0 10 20
30mA
0.2 0.4 3.3V 1.5 2.5 10
20
(10MHz)
5mA
3.6V 2.5 4.0 10 20 (1MHz)
PIN CONFIGURATION
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
(TOP VIEW)
1 23 456
A BC1# OE#
A0
A1
A2 S2
B DQ16 BC2#
A3
A4 S1# DQ1
C DQ14 DQ15
A5
A6 DQ2 DQ3
D GND DQ13
A17
A7 DQ4 VCC
E VCC
DQ12
NC or
GND
A16
DQ5 GND
F DQ11 DQ10 A14 A15 DQ7 DQ6
G DQ9
N.C. A12
A13 W#
DQ8
H N C A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
*Don't connect E3 ball to voltage level more than 0V.
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1# Chip select input 1
S2 Chip select input 2
W# Write control input
OE#
BC1#
Output enable input
Lower By te (DQ1 ~ 8)
BC2# Upper By te (DQ9 ~ 16)
Vcc Power supply
GND
Ground supply
1




M5M5V416CWG-55HI pdf, 반도체, 판매, 대치품
2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless noted. )
(1) TEST CONDITIONS
Supply v oltage
2.7~3.6V
Input pulse
VIH=2.4V, VIL=0.2V
Input rise time and f all time 5ns
Ref erence lev el
V OH=V OL= 1 . 5 0 V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
DQ
1TTL
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1# high
Output disable time af t er S2 low
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
(3) WRITE CYCLE
Symbol
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
Limits
5 5 HI
Min Max
55
55
55
55
55
55
30
20
20
20
20
20
10
10
5
5
5
10
Limits
70HI
Min Max
70
70
70
70
70
70
35
25
25
25
25
25
10
10
5
5
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
5 5 HI
Min Max
55
45
0
50
50
50
50
50
30
0
0
20
20
5
5
Limits
70HI
Min Max
70
55
0
60
60
60
60
60
35
0
0
25
25
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4

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M5M5V416CWG-55HI 전자부품, 판매, 대치품
2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
tCW
A 0~17
BC1#,BC2#
S1#
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S2
(Note3)
(Note5)
W#
(Note3)
DQ1~16
Write cycle (S2 control mode)
A 0~17
BC1#,BC2#
S1#
(Note3)
tsu (A)
(Note4)
tsu (D) th (D)
DATAIN
STABLE
tCW
tsu (S2)
trec (W)
(Note3)
(Note3)
(Note3)
S2
W#
DQ1~16
(Note3)
(Note5)
(Note3)
(Note4)
tsu (D) th (D)
DATAIN
STABLE
(Note3)
(Note3)
7

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M5M5V416CWG-55HI

CMOS STATIC RAM

Renesas Technology
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