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LFEC15 데이터시트 PDF




Lattice Semiconductor에서 제조한 전자 부품 LFEC15은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 LFEC15 자료 제공

부품번호 LFEC15 기능
기능 (LFEC Series) LatticeECP/EC Family Data Sheet
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


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LFEC15 데이터시트, 핀배열, 회로
www.DataSheet4U.com
LatticeECP/EC Family Data Sheet
Version 01.3




LFEC15 pdf, 반도체, 판매, 대치품
LatticeECP/EC Family Data Sheet
Architecture
November 2004
Preliminary Data Sheet
Architecture Overview
The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by Programma-
ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM
(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks as
shown in Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for exibility allowing complex designs to be implemented quickly and efciently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be congured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be congured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device conguration. The LatticeECP/EC devices use 1.2V as their core volt-
age.
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
2-1
Architecture_01.3

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LFEC15 전자부품, 판매, 대치품
Lattice Semiconductor
Figure 2-4. Slice Diagram
A1
B1
C1
D1
From
Routing
M1
M0
A0
B0
C0
D0
Architecture
LatticeECP/EC Family Data Sheet
To / From
Different slice / PFU
CO
LUT4 &
CARRY
F
SUM
CI
Slice
D
FF/
Latch
CO
LUT
Expansion
Mux
LUT4 & F
CARRY SUM OFX0
CI
D
FF/
Latch
OFX1
F1
Q1
To
Routing
OFX0
F0
Q0
Control Signals
selected and
inverted per
slice in routing
CE
CLK
LSR
Interslice signals
are not shown
To / From
Different slice / PFU
Table 2-1. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0 Multipurpose Input
Input
Multi-purpose
M1 Multipurpose Input
Input
Control signal
CE Clock Enable
Input
Control signal
LSR Local Set/Reset
Input
Control signal
CLK System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In1
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Register Outputs
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output
Inter-PFU signal
FCO
For the right most PFU the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4

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