ATF1508AE Datasheet PDF - ATMEL Corporation
| Part Number | ATF1508AE | |
| Description | (ATF15xxAE) 2nd Generation EE Complex Programmable Logic Devices | |
| Manufacturers | ATMEL Corporation | |
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Features
• 2nd Generation EE Complex Programmable Logic Devices
– 3.0V to 3.6V Operating Range with 5V Tolerant I/Os
– 32 - 512 Macrocells with Enhanced Features
– Pin-compatible with Industry-standard Devices
– Speeds to 4.5 ns Maximum Pin-to-pin Delay
– Registered Operation to 225 MHz
• Enhanced Macrocells with Logic Doubling™ Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade
Logic, Plus 15 More with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
• Enhanced Connectivity
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
• Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for µA Level Standby Current on “L” versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA
• EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature
ATF15xxAE
Family
Datasheet
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
Preliminary
Rev. 2398E–12/01
1
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ATF15xxAE Family
Figure 2. ATF15xxAE Family Macrocell with Enhanced Features In Red
SWITCH REGIONAL
MATRIX FOLDBACK
CASIN
OUTPUTS
BUS
LOGIC
FOLDBACK
80 16
40
1
PT1
PT2
PT3
GOE[0:5]
6
2
3
4
GOE [0:5]
SMWGAOTITRECIXH
5
Q
!Q
PT4
PT5
GCK[0:2]
I/O Pin
3
AP
D/T*/L
Q
CK/CK/LE
CE
AR
!Q
GCLEAR
I/O Pin
SLEW
RATE
OPEN
COLLECTOR
GLOBAL BUS
CASOUT
Reduced Power Option
* T flip-flop synthesised
Product Terms and
Select Mux
Within each macrocell are five product terms. Each product term may receive as its inputs any
combination of the signals from the switch matrix or regional foldback bus. The product term
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is determined by the fitter software,
which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can
be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK-
type flip-flops, or fed to the buried feedback to synthesize an extra latch.
Foldback Bus
Each macrocell can also generate a foldback product term. This signal goes to the regional
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms
in each region can also generate additional fan-in sum terms with nominal additional delay.
2398E–12/01
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ATF1508AE electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ATF1508AE.PDF Datasheet ] | |
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