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PDF ATF1504BE Data sheet ( Hoja de datos )
| Número de pieza | ATF1504BE | |
| Descripción | High Speed CPLD | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
– SSTL2-1 and SSTL3-1 Receiver
• In-System Programming (ISP) Supported
– 1.8V ISP Using IEEE 1532 (JTAG) Interface
– Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a Combinatorial Output and
Vice Versa
• Fully Green (RoHS Compliant)
• 10 µA Standby
• Power Saving Option During Operation Using PD1, PD2 Pins
• Programmable Pin-keeper Option on Inputs and I/Os
• Programmable Schmitt Trigger Option on Input and I/O Pins
• Programmable Input and I/O Pull-up Option (per Pin)
• Unused Pins Can Be Configured as Ground (Optional)
• Available in Commercial and Industrial Temperature Ranges
• Available in 100-lead TQFP
• Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• Security Fuse Feature
• Hot-Socketing Supported
High-
performance
CPLD
ATF1504BE
3637A–PLD–11/06
1 page  
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Figure 1-3. Block Diagram
8 or 16
8 or 16
ATF1504BE
I/O (MC64)/GCLK3
3637A–PLD–11/06
Each of the 64 macrocells generates a buried feedback signal that goes to the global bus (see
Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1504BE allows fast, efficient generation of complex logic functions. The ATF1504BE con-
tains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1504BE macrocell, shown in Figure 1-4, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1504BE. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project name,
part number, revision or date. The User Signature is accessible regardless of the state of the
security fuse.
The ATF1504BE device is an In-System Programming (ISP) device. It uses the industry-stan-
dard 4-pin JTAG interface (IEEE Std. 1532), and is fully compliant with JTAG’s Boundary-scan
Description Language (BSDL). ISP allows the device to be programmed without removing it from
the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design
modifications to be made in the field via software.
5
5 Page 
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ATF1504BE
5.1 In-System Configuration – ISC (Also Referred to as ISP)
This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The
term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP elim-
inates the need for an external device programmer, and the devices can be soldered to a PCB
without being preprogrammed.
In the ISC mode, the logic operation of the ATF1504BE is halted and the embedded configura-
tion memory is programmed. The device is programmed by first erasing the configuration
memory in the CPLD and loading the new configuration data into the memory, which in-turn con-
figures the PLD for functional mode. When the device is in the ISC programming mode, all user
I/Os are held in the high impedance state.
The ISC mode is best suited for working with the ATF1504BE device in a design development or
production environment. Configuration of the ATF1504BE device done via a Download Cable
(see Figure 5-1 on page 11) is the default mode used to program the device in the ISC mode. In
this mode, the PC is typically the controlling device that communicates with the CPLD.
Figure 5-1.
Configuration of ATF1504BE Device Using a Download Cable
ATF1504BE
CPLD Device
TCK
TDO
TMS
TDI
Connect
ISP Download
Cable to 10-pin
JTAG Header
VCC
12
34
56
78
9 10
JTAG
Connector
5.2 On-the-Fly Reconfiguration – OTF
In this mode, the CPLD design pattern stored in the internal configuration memory can be modi-
fied while the previous design pattern is operating with minimal disturbance to the operation of
the current design. The new configuration will take affect after the OTF programming process is
completed and the OTF mode is exited.
The configuration data for any design is stored in the internal configuration memory. Once the
configuration data is transferred to the internal static registers of the CPLD, the CPLD operates
with the design pattern and the configuration memory is free to be re-loaded with a new set of
configuration data. The design pattern due to the new configuration content is activated through
an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence.
Figure 5-2 shows the electrical interface for configuration of the ATF1504BE device in the OTF
mode. The processor is the controlling device that communicates with the CPLD and uses con-
figuration data stored in the external memory to configure the CPLD.
3637A–PLD–11/06
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATF1504BE.PDF ] | |
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