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PDF SL1461 Data sheet ( Hoja de datos )
| Número de pieza | SL1461 | |
| Descripción | WIDEBAND PLL FM DEMODULATOR | |
| Fabricantes | Gec Plessey | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SL1461 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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www.DataSheet4U.com
SEPTEMBER 1993
PRELIMINARY INFORMATION
D.S. 3754 1.6
SL1461
WIDEBAND PLL FM DEMODULATOR
The SL1461 is a wideband PLL FM demodulator, intended
primarily for application in satellite tuners.
The device contains all elements necessary, with the
exception of external oscillator sustaining network and loop
feedback components, to form a complete PLL system
operating at frequencies up to 800MHz.
An AFC with window adjust is provided, whose output
signal can be used to correct for any frequency drift at the head
end local oscillator.
FEATURES
J Single chip PLL system for wideband FM
demodulation
J Simple low component count application
J Allows for application of threshold extension
J Fully balanced low radiation design
J High operating input sensitivity
J AGC detect and bias adjust
J 75W video output drive with low distortion
levels
J Dynamic self biasing analog AFC
J Full ESD protection *
* Normal ESD handling procedures should be observed
AFC PUMP
AFC WINDOW ADJUST
VEE
OSCILLATOR +
OSCILLATOR –
AGC BIAS
AGC OUTPUT
RF INPUT
1 16 AFC OUTPUT
2 15 VCC
3 14 VIDEO FEEDBACK +
4 13 VIDEO –
5 12 VIDEO +
6 11 VIDEO FEEDBACK –
7 10 VIDEO OUTPUT
8 9 RF INPUT
MP16
Fig. 1 Pin connections top view
APPLICATIONS
J Satellite receiver systems
J Data communications systems
ORDERING INFORMATION
SL1461S/KG/MPAS
AGC BIAS 6
8
RF INPUTS 9
AGC OUTPUT 7
4
LOCAL
OSCILLATOR
5
AFC WINDOW 2
ADJUST
Fig. 2 SL1461 block diagram
14 VIDEO
FEEDBACK +
12 VIDEO +
13 VIDEO –
11 VIDEO
FEEDBACK –
10 VIDEO
OUTPUT
1 AFC PUMP
16 AFC OUTPUT
1 page  
FUNCTIONAL DESCRIPTION
The SL1461 is a wideband PLL FM demodulator, optimised
for application in satellite receiver systems and requiring a
minimum external component count. It contains all the
elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the typical
application in Fig. 3.
The internal pin connections are contained in Fig.6/6a.
In normal applications the second satellite IF frequency of
typically 402 or 479.5MHz is fed to the RF preamplifier, which
has a working sensitivity of typically –40 dBm, depending on
application and layout. The preamplifier contains an RF level
detect circuit, which generates an AGC signal that can be used
for controlling the gain of the IF amplifier stages, so
maintaining a fixed level to the RF input of the SL1461, for
optimum threshold performance. The bias point of the AGC
circuit can be adjusted to cater for variation in AGC line voltage
requirement and device input power. The typical AGC curves
DESIGN OF PLL LOOP PARAMETERS
SL1461
are shown in Fig. 9.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which is
generated by an on–board oscillator. The oscillator block uses
an external varactor tuned sustaining network and is
optimised for high linearity over the normal deviation range. A
typical frequency versus voltage characteristic for the
oscillator is contained in Fig. 7. The loop output is designed to
compensate for first order temperature variation effects; the
typical stability is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential
or single ended mode; if the appropriate phase detector gains
are assumed in calculating loop filters, both modes should
give the same loop response.
The loop amplifier drives a 75W output impedance buffer
amplifier, which can either be connected to a 75W load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
RF INPUT
GAIN = KD VOLT/RAD
R1
R2 C1
BASEBAND OUTPUT
VCO
GAIN = K0 RAD SEC/VOLT
Fig. 4
The SL1461 is normally used as a type 1 second order loop
and can be represented by the above diagram. For such a
system the following parameters apply;
t1 + C1.R1
t2 + C1.R2
and
t1
+
K0KD
w2n
t2
+
2z
wn
where:
K0 is the VCO gain in radian seconds per volt
KD is the phase detector gain in volts per radian
wn is the natural loop bandwidth
z is the loop damping factor
R1 is loop amplifier input impedance
Note: KO is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
From these factors the loop 3dB bandwidth can be determined
from the following expression;
w23dB + w2n(2z2 ) 1) " w2n Ǹ(2z2 ) 1)2 ) 1
Which approximates to
w3dB
+
2wnĂĂwhenĂĂz
+
1
Ǹ2
5
5 Page 
SL1461
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SL1461.PDF ] | |
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