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PESD5V0S1BB 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PESD5V0S1BB은 전자 산업 및 응용 분야에서
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부품번호 PESD5V0S1BB 기능
기능 Low capacitance bidirectional ESD protection diodes
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PESD5V0S1BB 데이터시트, 핀배열, 회로
www.DataSheet4U.com
DISCRETE SEMICONDUCTORS
DATA SHEET
M3D319
PESD5V0S1BB
Low capacitance bi-directional ESD
protection diode in SOD523
package
Product specification
2004 Mar 04




PESD5V0S1BB pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Philips Semiconductors
Low capacitance bi-directional ESD
protection diode in SOD523 package
Product specification
PESD5V0S1BB
120
handbook, halfpage
Ipp
(%)
80
40
100 % Ipp; 8 µs
MLE218
et
50 % Ipp; 20 µs
0
0 10 20 30 40
t (µs)
Ipp
100 %
90 %
001aaa191
10 %
tr = 0.7 to 1 ns
30 ns
60 ns
t
Fig.2 8/20 µs pulse waveform according to
IEC 61000-4-5.
Fig.3 ElectroStatic Discharge (ESD) pulse
waveform according to IEC 61000-4-2.
ELECTRICAL CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Per diode
VRWM
IRM
VBR
Cd
V(CL)R
rdiff
reverse stand-off voltage
reverse leakage current
breakdown voltage
diode capacitance
clamping voltage
differential resistance
VRWM = 5 V
IZ = 1 mA
f = 1 MHz; VR = 0 V
notes 1 and 2
Ipp = 1 A
Ipp = 12 A
IR = 1 mA
5.5
Notes
1. Non-repetitive current pulse 8/20 µs exponential decay waveform, see Fig.2.
2. Measured between pins 1 and 2.
TYP.
5
35
MAX. UNIT
5V
100 nA
9.5 V
45 pF
10 V
14 V
50
2004 Mar 04
4

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PESD5V0S1BB 전자부품, 판매, 대치품
www.DataSheet4U.com
Philips Semiconductors
Low capacitance bi-directional ESD
protection diode in SOD523 package
Product specification
PESD5V0S1BB
APPLICATION INFORMATION
The PESD5V0S1BB is designed for the bi-directional protection of one data line from the damage caused by
ElectroStatic Discharge (ESD) and surge pulses. The PESD5V0S1BB may be used on lines where the signal polarities
are above or below ground. PESD5V0S1BB can withstand and provides protection from a surge of 130 watt peak pulse
power surge per line for a 8/20 µs waveform.
Typical application
signal line
PESD5V0S1BB
GND
001aaa206
Fig.9 Typical application for bi-directional
protection of one line.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The
following guidelines are recommended:
1. The protection device should be placed as closely as possible to the input terminal or connector.
2. The path length between the protection device and the protected line should be as short as possible.
3. Parallel signal paths should be kept to a minimum.
4. Running protected conductors in parallel with unprotected conductors should be avoided.
5. All printed-circuit board conductive loops (including power and group loops) should be kept to a minimum.
6. The length of the transient return path to ground should be kept to a minimum.
7. The use of shared transient return paths to a common ground point should be avoided.
8. Ground planes should be used whenever possible.
9. For multilayer printed-circuit boards, ground vias should be used.
2004 Mar 04
7

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