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PDF W523Axxx Data sheet ( Hoja de datos )
| Número de pieza | W523Axxx | |
| Descripción | HIGH FIDELITY POWER SPEECH | |
| Fabricantes | Winbond | |
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W523AXXX
HIGH FIDELITY PowerSpeechTM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. BLOCK DIAGRAM ...................................................................................................................... 3
4. PIN DESCRIPTION..................................................................................................................... 4
5. FUNCTIONAL DESCRIPTION.................................................................................................... 5
5.1 Register Definition and Control........................................................................................ 5
5.2 Option Control Function................................................................................................... 8
5.3 Interrupt Vector Allocation ............................................................................................... 8
5.4 CPU Interface ................................................................................................................ 10
6. ELECTRICAL CHARACTERISTICS......................................................................................... 13
6.1 Absolute Maximum Ratings........................................................................................... 13
6.2 DC Characteristics......................................................................................................... 13
6.3 AC Characteristics......................................................................................................... 14
7. BONDING PAD DIAGRAM ....................................................................................................... 15
8. TYPICAL APPLICATION CIRCUIT........................................................................................... 17
8.1 DAC Output ................................................................................................................... 17
8.2 PWM Output .................................................................................................................. 18
9. REVISION HISTORY ................................................................................................................ 19
Publication Release Date: May 20, 2003
- 1 - Revision A3
1 page  
W523AXXX
5. FUNCTIONAL DESCRIPTION
I/O pins:
The W523Axxx family provides up to 4 trigger pins, which can be extended to 24 matrix trigger inputs,
up to 5 STOP output pins and up to 2 LED output pins. All of these I/O pins’ status can be easily
defined by PowerSpeech program.
Powerful programmable features:
The W523Axxx family provides JUMP (JP), LOAD (LD), MOVE (MV), INC, and END commands and
10 programmable registers, such as R0 ~ R3, EN0, EN1, MODE0, MODE1, STOP and PAGE, can be
easily used to program the desired playing mode, stop output signal form, LED flash type, and trigger
pin interrupt modes. The chip’s programmable features can also be used to develop new, customized
functions for a wide variety of innovative applications.
Programmable Power-on Initialization:
Whenever the W523Axxx is powered on or pressed the RESET pin, the program contained in the
32nd voice group will be executed after the power-on delay (about 160 mS), so the user can write a
program into this group to set the power-on initial state. If user does not wish to execute a program at
power-on, an “END” instruction should be entered in the group 32.
The interruption priority is shown as below while other trigger pins as well as JUMP (JP) command are
executing simultaneously during POI executing period:
POI > TG1F > TG1R > TG2F > TG2R > *TG5F > *TG5R > *TG6F > *TG6R > "JP" instruction.
*: TG3, TG4 for W523A008, W523A010
5.1 Register Definition and Control
The register file in the W523Axxx family is composed of 10 registers, including 4 general-purpose
registers and 6 special purpose registers. They are defined to facilitate the operations for various
purposes. The default setting values of the registers are given in the following table.
REGISTER
General Register
Special Register
NAME
R0-R3
EN0 (W523A008~A010)
EN0 (W523A012~A120)
EN1 (W523A012~A120)
MODE0, MODE1
STOP
PAGE
DEFAULT SETTING
00100000B
11111111B
XX11XX11B
XX11XX11B
11111111B
XXX11111B
00000000B
Publication Release Date: May 20, 2003
- 5 - Revision A3
5 Page 
W523AXXX
To place the W523Axxx in CPU mode, program the code according to the following example.
W523A015
CPU; Reserved word, used as a directive to notify the compiler for post processing.
LED1
FREQ2
POI:
LD MODE0,XX1XX0XXB
LD EN0, 0x00
H5+voice1+T5
END
;bit2=0 BUSY
34: ; Direct trigger or CPU interrupt.
H5+voice2+T5
END
The defaulted operating mode in W523Axxx is normal mode (or manual trigger mode), which is
identified by the "Normal" and "CPU" option control. To enter the CPU mode, the "CPU" declaration
must be inserted in the declaration region of program (*.out). In CPU mode, the bit MODE0.2, which is
defined as STPA or BUSY selection for the STPA/BUSY pin, will be selected as "0" (BUSY output)
automatically by the compiler unless otherwise specified explicitly by the STPA directive. The CPU,
STPA, and BUSY directives can appear only in the first paragraph of the *.out files so that the
compiler will automatically interpret them as Stop definitions in the POI interrupt vector. If these
directives are placed elsewhere, an error message will be issued during the compilation process.
In the program example shown above, the external µC will transfer one byte data "34" to W523Axxx.
The number 34 (Decimal) is equal to 00100010b (Binary). The interface timing is shown below.
TG1
(Data)
<1>
<2>
LSB MSB
01000100
<3> <4>
TG2
(Clock)
TDEB
TCRD
<1> When TG1 is pulled low, the W523Axxx stops playing voice or executing instruction and waits for data from
the external µC.
<2> If TG1 is debounced OK, the W523Axxx will clear the CPU receiving buffer.
<3> 8-bit data are transferred by TG1 (Data) and TG2 (Clock). LSB is sent firstly.
<4> TG1 returns to high and starts the CPU interrupt service. In this case W523A015 will play the
H51+voice2+T51 sections and the STPA/BUSY pin is pulled high during the playing period.
- 11 -
Publication Release Date: May 20, 2003
Revision A3
11 Page | ||
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