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PDF 74AUP1G885 Data sheet ( Hoja de datos )
| Número de pieza | 74AUP1G885 | |
| Descripción | Low Power Dual Function Gate | |
| Fabricantes | NXP Semiconductors | |
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74AUP1G885
Low-power dual function gate
Rev. 01 — 1 December 2006
Product data sheet
1. General description
The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G885 provides two functions in one device.The output state of the outputs
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean
function: 1Y = A × C. The output 2Y provides the boolean function: 2Y = A × B + A × C.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114D Class 3A exceeds 4000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
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NXP Semiconductors
74AUP1G885
Low-power dual function gate
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
VOH HIGH-level output voltage
VOL LOW-level output voltage
II
IOFF
∆IOFF
ICC
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
∆ICC
additional supply current
CI input capacitance
CO output capacitance
Tamb = −40 °C to +85 °C
VIH HIGH-level input voltage
VIL LOW-level input voltage
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC − 0.1 -
0.75 × VCC -
1.11 -
1.32 -
2.05 -
1.9 -
2.72 -
2.6 -
--
--
--
--
--
--
--
--
--
--
--
--
[1] -
-
- 0.8
- 1.7
0.70 × VCC -
0.65 × VCC -
1.6 -
2.0 -
--
--
--
--
Max Unit
-V
-V
-V
-V
-V
-V
-V
-V
0.1
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
V
µA
µA
µA
0.5 µA
40 µA
- pF
- pF
-V
-V
-V
-V
0.30 × VCC V
0.35 × VCC V
0.7 V
0.9 V
74AUP1G885_1
Product data sheet
Rev. 01 — 1 December 2006
© NXP B.V. 2006. All rights reserved.
5 of 17
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NXP Semiconductors
74AUP1G885
Low-power dual function gate
VCC
VEXT
PULSE
GENERATOR
VI
DUT
VO
5 kΩ
RT CL RL
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
0.8 V to 3.6 V
Load
CL RL[1]
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
VEXT
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1G885_1
Product data sheet
Rev. 01 — 1 December 2006
© NXP B.V. 2006. All rights reserved.
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