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PDF KSZ8999 Data sheet ( Hoja de datos )
| Número de pieza | KSZ8999 | |
| Descripción | Integrated 9-Port 10/100 Switch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KS8999
www.DataSheet4U.com
Micrel
KS8999
Integrated 9-Port 10/100 Switch with PHY and Frame Buffer
Rev. 1.14
General Description
The KS8999 contains eight 10/100 physical layer transceiv-
ers, nine MAC (Media Access Control) units with an inte-
grated layer 2 switch. The device runs in two modes. The first
mode is an eight port integrated switch and the second is as
a nine port switch with the ninth port available through an MII
(Media Independent Interface). Useful configurations include
a stand alone eight port switch as well as a eight port switch
with a routing element connected to the extra MII port. The
additional port is also useful for a public network interfacing.The
KS8999 is designed to reside in an unmanaged design not
requiring processor intervention. This is achieved through
I/O strapping or EEPROM programming at system reset
time.On the media side, the KS8999 supports 10BaseT,
100BaseTX and 100BaseFX as specified by the IEEE 802.3
committee. Physical signal transmission and reception are
enhanced through use of analog circuitry that makes the
design more efficient and allows for lower power consump-
tion and smaller chip die size.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Functional Diagram
Look Up
Engine
(1K Entries)
Queue Priority
Management
Buffer
Management
SRAM
Buffers
FIFO, Flow Control, VLAN and Priority
M
A
C
MM
A A MMMMMM
C C AA AAAA
CCCCCC
1
23
4
56 7 8 9
P
H
P
H
P
H
P
Y YYH
Y
1 23
4
EEPROM /
Processor
Interface
SCL
SDA
PPPP
HHHH
YYYY
5678
LED
and
Programming
Interface
LED[1][3:0]
LED[2][3:0]
LED[3][3:0]
LED[4][3:0]
LED[5][3:0]
LED[6][3:0]
LED[7][3:0]
LED[8][3:0]
LED[9][3:0]
M
I
I
MII /
SNI
(exclusive)
External
Interface
S
N
I
MRXD[3:0]
MRXDV
MCOL
MCRS
MTXD[3:0]
MTXEN
MTXER
MTXC
MRXC
MRXD[0]
MRXDV
MCOL
MTXD[0]
MTXEN
MTXC
MRXC
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2005
1
KS8999
1 page  
KS8999
Micrel
EEPROM Memory Map .............................................................................................................................................. 29
General Conrol Register .............................................................................................................................. 29
Priority Classification Control: 802.1p Tag Field ......................................................................................... 29
Port 1 Control Register ................................................................................................................................ 29
Port 2 Control Register ................................................................................................................................ 30
Port 3 Control Register ................................................................................................................................ 30
Port 4 Control Register ................................................................................................................................ 30
Port 5 Control Register ................................................................................................................................ 31
Port 6 Control Register ................................................................................................................................ 31
Port 7 Control Register ................................................................................................................................ 32
Port 8 Control Register ................................................................................................................................ 32
Port 9 Control Register ................................................................................................................................ 32
Port 1 VLAN Mask Register ......................................................................................................................... 33
Port 2 VLAN Mask Register ......................................................................................................................... 33
Port 3 VLAN Mask Register ......................................................................................................................... 34
Port 4 VLAN Mask Register ......................................................................................................................... 34
Port 5 VLAN Mask Register ......................................................................................................................... 35
Port 6 VLAN Mask Register ......................................................................................................................... 35
Port 7 VLAN Mask Register ......................................................................................................................... 36
Port 8 VLAN Mask Register ......................................................................................................................... 36
Port 9 VLAN Mask Register ......................................................................................................................... 37
Port 1 VLAN Tag Insertion Value Registers ................................................................................................. 37
Port 2 VLAN Tag Insertion Value Registers ................................................................................................. 37
Port 3 VLAN Tag Insertion Value Registers ................................................................................................. 37
Port 4 VLAN Tag Insertion Value Registers ................................................................................................. 37
Port 5 VLAN Tag Insertion Value Registers ................................................................................................. 38
Port 6 VLAN Tag Insertion Value Registers ................................................................................................. 38
Port 7 VLAN Tag Insertion Value Registers ................................................................................................. 38
Port 8 VLAN Tag Insertion Value Registers ................................................................................................. 38
Port 9 VLAN Tag Insertion Value Registers ................................................................................................. 38
Diff Serve Code Point Registers .................................................................................................................. 38
Station MAC Address Registers .................................................................................................................. 38
Absolute Maximum Ratings ..................................................................................................................................... 39
Operating Ratings ..................................................................................................................................................... 39
Electrical Characteristics (KS8999) ......................................................................................................................... 39
Electrical Characteristics (KS8999I) ........................................................................................................................ 41
Timing Diagrams ....................................................................................................................................................... 42
Reference Circuit ....................................................................................................................................................... 47
4B/5B Coding ........................................................................................................................................................... 49
MLT Coding ........................................................................................................................................................... 50
MAC Frame ........................................................................................................................................................... 50
Selection of Isolation Transformers ........................................................................................................................ 51
Selection of Reference Oscillator/Crystal ............................................................................................................... 51
Qualified Magnetic Lists ........................................................................................................................................... 51
Package Information ................................................................................................................................................. 52
January 2005
5
KS8999
5 Page 
KS8999
Pin Number
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
Pin Name Type(Note 1)
LED[5][0]
Ipu/O
LED[6][3]
Ipu/O
LED[6][2]
Ipu/O
LED[6][1]
Ipu/O
LED[6][0]
Ipu/O
LED[7][3]
Ipu/O
LED[7][2]
Ipu/O
LED[7][1]
Ipu/O
VDD-IO
Pwr
LED[7][0]
Ipu/O
LED[8][3]
Ipu/O
LED[8][2]
Ipu/O
LED[8][1]
Ipu/O
LED[8][0]
Ipu/O
GND
GND
GND
GND
IO_SWM
Ipu
VDD
Pwr
LED[9][3]
Ipu/O
LED[9][2]
Ipu/O
LED[9][1]
Ipu/O
LED[9][0]
Ipu/O
MIIS[1]
Ipd
MIIS[0]
Ipd
MODESEL[3]
Ipd
MODESEL[2]
Ipd
MODESEL[1]
Ipd
MODESEL[0]
Ipd
TESTEN
Ipd
SCANEN
Ipd
PRSV
Ipd
CFGMODE
Ipu
T[5] I
T[4] Ipdthevillage
Port
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
9
9
174 Reserve I
Pin Function
LED indicator 0
LED indicator 3
LED indicator 2
LED indicator 1
LED indicator 0
LED indicator 3
LED indicator 2
LED indicator 1
2.0V, 2.5V or 3.3V for I/O circuitry
LED indicator 0
LED indicator 3
LED indicator 2
LED indicator 1
LED indicator 0
Ground for digital circuitry
Ground for digital circuitry
Factory test pin – tie high for normal operation
2.0V for core digital circuitry
LED indicator 3
LED indicator 2
LED indicator 1
LED indicator 0
MII mode select bit 1
MII mode select bit 0
Selects LED and test modes
Selects LED and test modes
Selects LED and test modes
Selects LED and test modes
Factory test pin – tie low for normal operation
Factory test pin – tie low for normal operation
Reserve 6KB buffer for priority frames
Configures programming interface for EEPROM or processor
Factory test pin – float for normal operation
F/D = normal operation (default)
U = disable FEF
Reserved – floating for normal operation
Note 1.
Pwr = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Opu = output w/ internal pull-up
Opd = output w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
January 2005
11
Micrel
KS8999
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8999.PDF ] | |
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